[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32InstrInfo.cpp updated: 1.6 -> 1.7
---
Log message:

Fix a CQ regression from my patch to split F32/F64 into seperate register
classes on PPC.  We were emitting fmr instructions to do fp extensions, which
weren't getting coallesced.  This fixes Regression/CodeGen/PowerPC/fpcopy.ll


---
Diffs of the changes:  (+2 -1)

 PPC32InstrInfo.cpp |    3 ++-
 1 files changed, 2 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.6 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.7
--- llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.6	Fri Sep 30 20:34:18 2005
+++ llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp	Fri Oct  7 00:00:52 2005
@@ -57,7 +57,8 @@
       destReg = MI.getOperand(0).getReg();
       return true;
     }
-  } else if (oc == PPC::FMRS || oc == PPC::FMRD) {      // fmr r1, r2
+  } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
+             oc == PPC::FMRSD) {      // fmr r1, r2
     assert(MI.getNumOperands() == 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&