[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp PPC32ISelPattern.cpp PowerPCInstrInfo.td

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelDAGToDAG.cpp updated: 1.92 -> 1.93
PPC32ISelPattern.cpp updated: 1.182 -> 1.183
PowerPCInstrInfo.td updated: 1.116 -> 1.117
---
Log message:

another solution to the fsel issue.  Instead of having 4 variants, just force
the comparison to be 64-bits.  This is fine because extensions from float
to double are free.


---
Diffs of the changes:  (+25 -32)

 PPC32ISelDAGToDAG.cpp |   20 ++++++++------------
 PPC32ISelPattern.cpp  |   15 +++++++++------
 PowerPCInstrInfo.td   |   22 ++++++++--------------
 3 files changed, 25 insertions(+), 32 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.92 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.93
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.92	Sun Oct  2 01:58:23 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Sun Oct  2 02:07:49 2005
@@ -753,18 +753,14 @@
     return SDOperand(Result.Val, Op.ResNo);
   }      
   case PPCISD::FSEL: {
-    unsigned Opc;
-    if (N->getValueType(0) == MVT::f32) {
-      Opc = N->getOperand(0).getValueType() == MVT::f32 ?
-              PPC::FSELSS : PPC::FSELSD;
-    } else {
-      Opc = N->getOperand(0).getValueType() == MVT::f64 ?
-              PPC::FSELDD : PPC::FSELDS;
-    }
-    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0),
-                         Select(N->getOperand(0)),
-                         Select(N->getOperand(1)),
-                         Select(N->getOperand(2)));
+    SDOperand Comparison = Select(N->getOperand(0));
+    // Extend the comparison to 64-bits.
+    if (Comparison.getValueType() == MVT::f32)
+      Comparison = CurDAG->getTargetNode(PPC::FMRSD, MVT::f64, Comparison);
+    
+    unsigned Opc = N->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
+    CurDAG->SelectNodeTo(N, Opc, N->getValueType(0), Comparison,
+                         Select(N->getOperand(1)), Select(N->getOperand(2)));
     return SDOperand(N, 0);
   }
   case PPCISD::FCFID:


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.182 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.183
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.182	Sun Oct  2 01:58:23 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sun Oct  2 02:07:49 2005
@@ -815,12 +815,15 @@
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
     Tmp3 = SelectExpr(N.getOperand(2));
-    if (N.getOperand(0).getValueType() == MVT::f32)
-      Opc = N.getOperand(0).getValueType() == MVT::f32 ?
-        PPC::FSELSS : PPC::FSELSD;
-    else
-      Opc = N.getOperand(0).getValueType() == MVT::f64 ?
-        PPC::FSELDD : PPC::FSELDS;
+
+    // Extend the comparison to 64-bits if needed.
+    if (N.getOperand(0).getValueType() == MVT::f32) {
+      unsigned Tmp1New = MakeReg(MVT::f64);
+      BuildMI(BB, PPC::FMRSD, 1, Tmp1New).addReg(Tmp1);
+      Tmp1 = Tmp1New;
+    }
+      
+    Opc = N.Val->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD;
     BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
     return Result;
   case PPCISD::FCFID:


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.116 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.117
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.116	Sun Oct  2 01:58:23 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Sun Oct  2 02:07:49 2005
@@ -791,21 +791,15 @@
                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
                     "fnmsubs $FRT, $FRA, $FRC, $FRB",
                     []>;
-// FSEL is artificially split into 4 and 8-byte forms for the comparison type
+// FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
+// having 4 of these, force the comparison to always be an 8-byte double (code
+// should use an FMRSD if the input comparison value really wants to be a float)
 // and 4/8 byte forms for the result and operand type..
-def FSELDD : AForm_1<63, 23,
-                     (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
-                     "fsel $FRT, $FRA, $FRC, $FRB",
-                     []>;
-def FSELSS : AForm_1<63, 23,
-                     (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
-                     "fsel $FRT, $FRA, $FRC, $FRB",
-                     []>;
-def FSELDS : AForm_1<63, 23,  // result Double, comparison Single
-                     (ops F8RC:$FRT, F4RC:$FRA, F8RC:$FRC, F8RC:$FRB),
-                     "fsel $FRT, $FRA, $FRC, $FRB",
-                     []>;
-def FSELSD : AForm_1<63, 23,  // result Single, comparison Double
+def FSELD : AForm_1<63, 23,
+                    (ops F8RC:$FRT, F8RC:$FRA, F8RC:$FRC, F8RC:$FRB),
+                    "fsel $FRT, $FRA, $FRC, $FRB",
+                    []>;
+def FSELS : AForm_1<63, 23,
                      (ops F4RC:$FRT, F8RC:$FRA, F4RC:$FRC, F4RC:$FRB),
                      "fsel $FRT, $FRA, $FRC, $FRB",
                      []>;