[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sat Oct 1 23:37:25 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelLowering.cpp updated: 1.28 -> 1.29
---
Log message:
fix an f32/f64 type mismatch
---
Diffs of the changes: (+6 -2)
PPC32ISelLowering.cpp | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.28 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.29
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.28 Fri Sep 30 20:35:02 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp Sun Oct 2 01:37:13 2005
@@ -130,13 +130,17 @@
default: assert(0 && "Wasn't expecting to be able to lower this!");
case ISD::FP_TO_SINT: {
assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
+ SDOperand Src = Op.getOperand(0);
+ if (Src.getValueType() == MVT::f32)
+ Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
+
switch (Op.getValueType()) {
default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
case MVT::i32:
- Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
+ Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
break;
case MVT::i64:
- Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
+ Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
break;
}
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