[llvm-commits] CVS: llvm/lib/CodeGen/PrologEpilogInserter.cpp RegAllocLocal.cpp RegAllocSimple.cpp VirtRegMap.cpp
Chris Lattner
lattner at cs.uiuc.edu
Thu Sep 29 18:29:12 PDT 2005
Changes in directory llvm/lib/CodeGen:
PrologEpilogInserter.cpp updated: 1.46 -> 1.47
RegAllocLocal.cpp updated: 1.73 -> 1.74
RegAllocSimple.cpp updated: 1.64 -> 1.65
VirtRegMap.cpp updated: 1.39 -> 1.40
---
Log message:
Change this code ot pass register classes into the stack slot spiller/reloader
code. PrologEpilogInserter hasn't been updated yet though, so targets cannot
use this info.
---
Diffs of the changes: (+19 -11)
PrologEpilogInserter.cpp | 6 ++++--
RegAllocLocal.cpp | 4 ++--
RegAllocSimple.cpp | 4 ++--
VirtRegMap.cpp | 16 +++++++++++-----
4 files changed, 19 insertions(+), 11 deletions(-)
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.46 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.47
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.46 Sun Aug 28 19:10:46 2005
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Thu Sep 29 20:29:00 2005
@@ -200,7 +200,8 @@
MachineBasicBlock::iterator I = MBB->begin();
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
// Insert the spill to the stack frame.
- RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+ RegInfo->storeRegToStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+ 0 /*FIXME*/);
}
// Add code to restore the callee-save registers in each exiting block.
@@ -225,7 +226,8 @@
// Restore all registers immediately before the return and any terminators
// that preceed it.
for (unsigned i = 0, e = RegsToSave.size(); i != e; ++i) {
- RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i]);
+ RegInfo->loadRegFromStackSlot(*MBB, I, RegsToSave[i], StackSlots[i],
+ 0 /*FIXME*/);
assert(I != MBB->begin() &&
"loadRegFromStackSlot didn't insert any code!");
// Insert in reverse order. loadRegFromStackSlot can insert multiple
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.73 llvm/lib/CodeGen/RegAllocLocal.cpp:1.74
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.73 Tue Aug 23 18:42:17 2005
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Thu Sep 29 20:29:00 2005
@@ -270,7 +270,7 @@
const TargetRegisterClass *RC = MF->getSSARegMap()->getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DEBUG(std::cerr << " to stack slot #" << FrameIndex);
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex);
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIndex, RC);
++NumStores; // Update statistics
}
@@ -476,7 +476,7 @@
<< RegInfo->getName(PhysReg) << "\n");
// Add move instruction(s)
- RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex);
+ RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
PhysRegsEverUsed[PhysReg] = true;
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.64 llvm/lib/CodeGen/RegAllocSimple.cpp:1.65
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.64 Thu Apr 21 23:01:15 2005
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu Sep 29 20:29:00 2005
@@ -135,7 +135,7 @@
// Add move instruction(s)
++NumLoads;
- RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx);
+ RegInfo->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@@ -147,7 +147,7 @@
// Add move instruction(s)
++NumStores;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx);
+ RegInfo->storeRegToStackSlot(MBB, I, PhysReg, FrameIdx, RC);
}
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.39 llvm/lib/CodeGen/VirtRegMap.cpp:1.40
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.39 Mon Sep 19 01:56:21 2005
+++ llvm/lib/CodeGen/VirtRegMap.cpp Thu Sep 29 20:29:00 2005
@@ -163,18 +163,20 @@
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
+ const TargetRegisterClass* RC =
+ MF.getSSARegMap()->getRegClass(VirtReg);
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+ MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII));
}
if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+ MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
++NumStores;
}
}
@@ -386,6 +388,8 @@
// Otherwise, reload it and remember that we have it.
PhysReg = VRM.getPhys(VirtReg);
+ const TargetRegisterClass* RC =
+ MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
RecheckRegister:
// Note that, if we reused a register for a previous operand, the
@@ -406,7 +410,7 @@
// was used. This isn't good because it means we have
// to undo a previous reuse.
MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
- Op.StackSlot);
+ Op.StackSlot, RC);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);
@@ -431,7 +435,7 @@
}
ContinueReload:
PhysRegsUsed[PhysReg] = true;
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+ MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
// This invalidates PhysReg.
ClobberPhysReg(PhysReg, SpillSlotsAvailable, PhysRegsAvailable);
@@ -553,6 +557,8 @@
if (!TakenCareOf) {
// The only vregs left are stack slot definitions.
int StackSlot = VRM.getStackSlot(VirtReg);
+ const TargetRegisterClass *RC =
+ MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
unsigned PhysReg;
// If this is a def&use operand, and we used a different physreg for
@@ -564,7 +570,7 @@
PhysReg = MO.getReg();
PhysRegsUsed[PhysReg] = true;
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+ MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
DEBUG(std::cerr << "Store:\t" << *next(MII));
MI.SetMachineOperandReg(i, PhysReg);
More information about the llvm-commits
mailing list