[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td PowerPCInstrFormats.td
Chris Lattner
lattner at cs.uiuc.edu
Thu Sep 29 16:34:36 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PowerPCInstrInfo.td updated: 1.113 -> 1.114
PowerPCInstrFormats.td updated: 1.50 -> 1.51
---
Log message:
Add a bunch of patterns for F64 FP ops, add some more integer ops
---
Diffs of the changes: (+84 -38)
PowerPCInstrFormats.td | 19 +++++----
PowerPCInstrInfo.td | 103 ++++++++++++++++++++++++++++++++++---------------
2 files changed, 84 insertions(+), 38 deletions(-)
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.113 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.114
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.113 Thu Sep 29 17:37:24 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Thu Sep 29 18:34:24 2005
@@ -76,6 +76,9 @@
def SDTIntUnaryOp : SDTypeProfile<1, 1, [ // ctlz
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
+def SDTFPUnaryOp : SDTypeProfile<1, 1, [ // fneg, fsqrt, etc
+ SDTCisSameAs<0, 1>, SDTCisFP<0>
+]>;
def SDTExtInreg : SDTypeProfile<1, 2, [ // sext_inreg
SDTCisSameAs<0, 1>, SDTCisInt<0>, SDTCisVT<2, OtherVT>,
SDTCisVTSmallerThanOp<2, 1>
@@ -117,6 +120,9 @@
def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
+def srl : SDNode<"ISD::SRL" , SDTIntBinOp>;
+def sra : SDNode<"ISD::SRA" , SDTIntBinOp>;
+def shl : SDNode<"ISD::SHL" , SDTIntBinOp>;
def and : SDNode<"ISD::AND" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def or : SDNode<"ISD::OR" , SDTIntBinOp,
@@ -128,6 +134,9 @@
def fmul : SDNode<"ISD::FMUL" , SDTFPBinOp, [SDNPCommutative]>;
def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>;
def frem : SDNode<"ISD::FREM" , SDTFPBinOp>;
+def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>;
+def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>;
+def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>;
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def ctlz : SDNode<"ISD::CTLZ" , SDTIntUnaryOp>;
@@ -533,19 +542,19 @@
[]>, isPPC64;
def SLW : XForm_6<31, 24, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"slw $rA, $rS, $rB",
- []>;
+ [(set GPRC:$rA, (shl GPRC:$rS, GPRC:$rB))]>;
def SRD : XForm_6<31, 539, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srd $rA, $rS, $rB",
[]>, isPPC64;
def SRW : XForm_6<31, 536, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srw $rA, $rS, $rB",
- []>;
+ [(set GPRC:$rA, (srl GPRC:$rS, GPRC:$rB))]>;
def SRAD : XForm_6<31, 794, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srad $rA, $rS, $rB",
[]>, isPPC64;
def SRAW : XForm_6<31, 792, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"sraw $rA, $rS, $rB",
- []>;
+ [(set GPRC:$rA, (sra GPRC:$rS, GPRC:$rB))]>;
let isStore = 1 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stbx $rS, $rA, $rB">;
@@ -561,7 +570,8 @@
"stdux $rS, $rA, $rB">, isPPC64;
}
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
- "srawi $rA, $rS, $SH">;
+ "srawi $rA, $rS, $SH",
+ [(set GPRC:$rA, (sra GPRC:$rS, imm:$SH))]>;
def CNTLZW : XForm_11<31, 26, (ops GPRC:$rA, GPRC:$rS),
"cntlzw $rA, $rS",
[(set GPRC:$rA, (ctlz GPRC:$rS))]>;
@@ -597,25 +607,35 @@
"lfdx $dst, $base, $index">;
}
def FCFID : XForm_26<63, 846, (ops FPRC:$frD, FPRC:$frB),
- "fcfid $frD, $frB">, isPPC64;
+ "fcfid $frD, $frB",
+ []>, isPPC64;
def FCTIDZ : XForm_26<63, 815, (ops FPRC:$frD, FPRC:$frB),
- "fctidz $frD, $frB">, isPPC64;
+ "fctidz $frD, $frB",
+ []>, isPPC64;
def FCTIWZ : XForm_26<63, 15, (ops FPRC:$frD, FPRC:$frB),
- "fctiwz $frD, $frB">;
+ "fctiwz $frD, $frB",
+ []>;
def FABS : XForm_26<63, 264, (ops FPRC:$frD, FPRC:$frB),
- "fabs $frD, $frB">;
+ "fabs $frD, $frB",
+ [(set FPRC:$frD, (fabs FPRC:$frB))]>;
def FMR : XForm_26<63, 72, (ops FPRC:$frD, FPRC:$frB),
- "fmr $frD, $frB">;
+ "fmr $frD, $frB",
+ []>; // (set FPRC:$frD, FPRC:$frB)
def FNABS : XForm_26<63, 136, (ops FPRC:$frD, FPRC:$frB),
- "fnabs $frD, $frB">;
+ "fnabs $frD, $frB",
+ [(set FPRC:$frD, (fneg (fabs FPRC:$frB)))]>;
def FNEG : XForm_26<63, 40, (ops FPRC:$frD, FPRC:$frB),
- "fneg $frD, $frB">;
+ "fneg $frD, $frB",
+ [(set FPRC:$frD, (fneg FPRC:$frB))]>;
def FRSP : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
- "frsp $frD, $frB">;
+ "frsp $frD, $frB",
+ []>;
def FSQRT : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
- "fsqrt $frD, $frB">;
+ "fsqrt $frD, $frB",
+ [(set FPRC:$frD, (fsqrt FPRC:$frB))]>;
def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
- "fsqrts $frD, $frB">;
+ "fsqrts $frD, $frB",
+ []>;
let isStore = 1 in {
def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
@@ -711,55 +731,76 @@
//
def FMADD : AForm_1<63, 29,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmadd $FRT, $FRA, $FRC, $FRB">;
+ "fmadd $FRT, $FRA, $FRC, $FRB",
+ [(set FPRC:$FRT, (fadd (fmul FPRC:$FRA, FPRC:$FRC),
+ FPRC:$FRB))]>;
def FMADDS : AForm_1<59, 29,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmadds $FRT, $FRA, $FRC, $FRB">;
+ "fmadds $FRT, $FRA, $FRC, $FRB",
+ []>;
def FMSUB : AForm_1<63, 28,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmsub $FRT, $FRA, $FRC, $FRB">;
+ "fmsub $FRT, $FRA, $FRC, $FRB",
+ [(set FPRC:$FRT, (fsub (fmul FPRC:$FRA, FPRC:$FRC),
+ FPRC:$FRB))]>;
def FMSUBS : AForm_1<59, 28,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fmsubs $FRT, $FRA, $FRC, $FRB">;
+ "fmsubs $FRT, $FRA, $FRC, $FRB",
+ []>;
def FNMADD : AForm_1<63, 31,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmadd $FRT, $FRA, $FRC, $FRB">;
+ "fnmadd $FRT, $FRA, $FRC, $FRB",
+ [(set FPRC:$FRT, (fneg (fadd (fmul FPRC:$FRA, FPRC:$FRC),
+ FPRC:$FRB)))]>;
def FNMADDS : AForm_1<59, 31,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmadds $FRT, $FRA, $FRC, $FRB">;
+ "fnmadds $FRT, $FRA, $FRC, $FRB",
+ []>;
def FNMSUB : AForm_1<63, 30,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmsub $FRT, $FRA, $FRC, $FRB">;
+ "fnmsub $FRT, $FRA, $FRC, $FRB",
+ [(set FPRC:$FRT, (fneg (fsub (fmul FPRC:$FRA, FPRC:$FRC),
+ FPRC:$FRB)))]>;
def FNMSUBS : AForm_1<59, 30,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fnmsubs $FRT, $FRA, $FRC, $FRB">;
+ "fnmsubs $FRT, $FRA, $FRC, $FRB",
+ []>;
def FSEL : AForm_1<63, 23,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRC, FPRC:$FRB),
- "fsel $FRT, $FRA, $FRC, $FRB">;
+ "fsel $FRT, $FRA, $FRC, $FRB",
+ []>;
def FADD : AForm_2<63, 21,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadd $FRT, $FRA, $FRB">;
+ "fadd $FRT, $FRA, $FRB",
+ [(set FPRC:$FRT, (fadd FPRC:$FRA, FPRC:$FRB))]>;
def FADDS : AForm_2<59, 21,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fadds $FRT, $FRA, $FRB">;
+ "fadds $FRT, $FRA, $FRB",
+ []>;
def FDIV : AForm_2<63, 18,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdiv $FRT, $FRA, $FRB">;
+ "fdiv $FRT, $FRA, $FRB",
+ [(set FPRC:$FRT, (fdiv FPRC:$FRA, FPRC:$FRB))]>;
def FDIVS : AForm_2<59, 18,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fdivs $FRT, $FRA, $FRB">;
+ "fdivs $FRT, $FRA, $FRB",
+ []>;
def FMUL : AForm_3<63, 25,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmul $FRT, $FRA, $FRB">;
+ "fmul $FRT, $FRA, $FRB",
+ [(set FPRC:$FRT, (fmul FPRC:$FRA, FPRC:$FRB))]>;
def FMULS : AForm_3<59, 25,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fmuls $FRT, $FRA, $FRB">;
+ "fmuls $FRT, $FRA, $FRB",
+ []>;
def FSUB : AForm_2<63, 20,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsub $FRT, $FRA, $FRB">;
+ "fsub $FRT, $FRA, $FRB",
+ [(set FPRC:$FRT, (fsub FPRC:$FRA, FPRC:$FRB))]>;
def FSUBS : AForm_2<59, 20,
(ops FPRC:$FRT, FPRC:$FRA, FPRC:$FRB),
- "fsubs $FRT, $FRA, $FRB">;
+ "fsubs $FRT, $FRA, $FRB",
+ []>;
// M-Form instructions. rotate and mask instructions.
//
Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.50 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.51
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.50 Thu Sep 8 12:40:49 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td Thu Sep 29 18:34:24 2005
@@ -240,8 +240,9 @@
class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
: XForm_base_r3xo<opcode, xo, OL, asmstr>;
-class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
: XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> {
+ let Pattern = pt;
}
class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
@@ -290,9 +291,10 @@
: XForm_base_r3xo<opcode, xo, OL, asmstr> {
}
-class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt>
: XForm_base_r3xo<opcode, xo, OL, asmstr> {
let A = 0;
+ let Pattern = pt;
}
class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
@@ -463,13 +465,16 @@
}
// 1.7.12 A-Form
-class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
+class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr,
+ list<dag> pattern>
: I<opcode, OL, asmstr> {
bits<5> FRT;
bits<5> FRA;
bits<5> FRC;
bits<5> FRB;
+ let Pattern = pattern;
+
bit RC = 0; // set by isDOT
let Inst{6-10} = FRT;
@@ -480,13 +485,13 @@
let Inst{31} = RC;
}
-class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
- : AForm_1<opcode, xo, OL, asmstr> {
+class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
+ : AForm_1<opcode, xo, OL, asmstr, pat> {
let FRC = 0;
}
-class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr>
- : AForm_1<opcode, xo, OL, asmstr> {
+class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat>
+ : AForm_1<opcode, xo, OL, asmstr, pat> {
let FRB = 0;
}
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