[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
Chris Lattner
lattner at cs.uiuc.edu
Tue Sep 13 12:31:56 PDT 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.169 -> 1.170
---
Log message:
This code is no longer needed, it is moved to the target-indep code
---
Diffs of the changes: (+0 -24)
AlphaISelPattern.cpp | 24 ------------------------
1 files changed, 24 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.169 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.170
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.169 Tue Sep 6 12:00:23 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Tue Sep 13 14:31:44 2005
@@ -116,8 +116,6 @@
CCInvMap.clear();
}
- virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
-
unsigned SelectExpr(SDOperand N);
void Select(SDOperand N);
@@ -135,28 +133,6 @@
};
}
-void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
- // If this function has live-in values, emit the copies from pregs to vregs at
- // the top of the function, before anything else.
- MachineBasicBlock *BB = MF.begin();
- if (MF.livein_begin() != MF.livein_end()) {
- SSARegMap *RegMap = MF.getSSARegMap();
- for (MachineFunction::livein_iterator LI = MF.livein_begin(),
- E = MF.livein_end(); LI != E; ++LI) {
- const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
- if (RC == Alpha::GPRCRegisterClass) {
- BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first)
- .addReg(LI->first);
- } else if (RC == Alpha::FPRCRegisterClass) {
- BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first)
- .addReg(LI->first);
- } else {
- assert(0 && "Unknown regclass!");
- }
- }
- }
-}
-
static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
// test for constant
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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