[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td PPC32InstrInfo.h PPC32InstrInfo.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PowerPCInstrInfo.td updated: 1.96 -> 1.97
PPC32InstrInfo.h updated: 1.2 -> 1.3
PPC32InstrInfo.cpp updated: 1.4 -> 1.5
---
Log message:

Teach the code generator that rlwimi is commutable if the rotate amount
is zero.  This lets the register allocator elide some copies in some cases.

This implements CodeGen/PowerPC/rlwimi-commute.ll 


---
Diffs of the changes:  (+38 -1)

 PPC32InstrInfo.cpp  |   32 ++++++++++++++++++++++++++++++++
 PPC32InstrInfo.h    |    4 ++++
 PowerPCInstrInfo.td |    3 ++-
 3 files changed, 38 insertions(+), 1 deletion(-)


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.96 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.97
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.96	Thu Sep  8 19:39:56 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Fri Sep  9 13:17:41 2005
@@ -733,7 +733,8 @@
 
 // M-Form instructions.  rotate and mask instructions.
 //
-let isTwoAddress = 1 in {
+let isTwoAddress = 1, isCommutable = 1 in {
+// RLWIMI can be commuted if the rotate amount is zero.
 def RLWIMI : MForm_2<20,
                      (ops GPRC:$rA, GPRC:$rSi, GPRC:$rS, u5imm:$SH, u5imm:$MB, 
                       u5imm:$ME), "rlwimi $rA, $rS, $SH, $MB, $ME">;


Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.h
diff -u llvm/lib/Target/PowerPC/PPC32InstrInfo.h:1.2 llvm/lib/Target/PowerPC/PPC32InstrInfo.h:1.3
--- llvm/lib/Target/PowerPC/PPC32InstrInfo.h:1.2	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32InstrInfo.h	Fri Sep  9 13:17:41 2005
@@ -38,6 +38,10 @@
                            unsigned& sourceReg,
                            unsigned& destReg) const;
 
+  // commuteInstruction - We can commute rlwimi instructions, but only if the
+  // rotate amt is zero.  We also have to munge the immediates a bit.
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  
   static unsigned invertPPCBranchOpcode(unsigned Opcode) {
     switch (Opcode) {
     default: assert(0 && "Unknown PPC branch opcode!");


Index: llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.4 llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.5
--- llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp:1.4	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32InstrInfo.cpp	Fri Sep  9 13:17:41 2005
@@ -76,3 +76,35 @@
   }
   return false;
 }
+
+// commuteInstruction - We can commute rlwimi instructions, but only if the
+// rotate amt is zero.  We also have to munge the immediates a bit.
+MachineInstr *PPC32InstrInfo::commuteInstruction(MachineInstr *MI) const {
+  // Normal instructions can be commuted the obvious way.
+  if (MI->getOpcode() != PPC::RLWIMI)
+    return TargetInstrInfo::commuteInstruction(MI);
+  
+  // Cannot commute if it has a non-zero rotate count.
+  if (MI->getOperand(3).getImmedValue() != 0)
+    return 0;
+  
+  // If we have a zero rotate count, we have:
+  //   M = mask(MB,ME)
+  //   Op0 = (Op1 & ~M) | (Op2 & M)
+  // Change this to:
+  //   M = mask((ME+1)&31, (MB-1)&31)
+  //   Op0 = (Op2 & ~M) | (Op1 & M)
+
+  // Swap op1/op2
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(2).getReg();
+  MI->SetMachineOperandReg(2, Reg1);
+  MI->SetMachineOperandReg(1, Reg2);
+  
+  // Swap the mask around.
+  unsigned MB = MI->getOperand(4).getImmedValue();
+  unsigned ME = MI->getOperand(5).getImmedValue();
+  MI->getOperand(4).setImmedValue((ME+1) & 31);
+  MI->getOperand(5).setImmedValue((MB-1) & 31);
+  return MI;
+}