[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelLowering.cpp AlphaISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelLowering.cpp updated: 1.1 -> 1.2
AlphaISelPattern.cpp updated: 1.167 -> 1.168
---
Log message:

revert part of the last change, should fix regressions

---
Diffs of the changes:  (+11 -6)

 AlphaISelLowering.cpp |   12 ++++++------
 AlphaISelPattern.cpp  |    5 +++++
 2 files changed, 11 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelLowering.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.1 llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.2
--- llvm/lib/Target/Alpha/AlphaISelLowering.cpp:1.1	Fri Sep  2 13:46:02 2005
+++ llvm/lib/Target/Alpha/AlphaISelLowering.cpp	Sun Sep  4 01:12:19 2005
@@ -131,9 +131,9 @@
   MachineBasicBlock& BB = MF.front();
   std::vector<SDOperand> ArgValues;
 
-  static const unsigned args_int[] = {
+  unsigned args_int[] = {
     Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
-  static const unsigned args_float[] = {
+  unsigned args_float[] = {
     Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
   unsigned added_int = 0;
   unsigned added_fp = 0;
@@ -155,7 +155,7 @@
         abort();
       case MVT::f64:
       case MVT::f32:
-        MF.addLiveIn(args_float[count]);
+        args_float[count] = AddLiveIn(MF, args_float[count], getRegClassFor(VT));
         added_fp |= (1 << count);
         argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
         DAG.setRoot(argt.getValue(1));
@@ -165,7 +165,7 @@
       case MVT::i16:
       case MVT::i32:
       case MVT::i64:
-        MF.addLiveIn(args_int[count]);
+        args_int[count] = AddLiveIn(MF, args_int[count], getRegClassFor(MVT::i64));
         added_int |= (1 << count);
         argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
         DAG.setRoot(argt.getValue(1));
@@ -198,7 +198,7 @@
     std::vector<SDOperand> LS;
     for (int i = 0; i < 6; ++i) {
       if (!(added_int & (1 << i)))
-        MF.addLiveIn(args_int[i]);
+        args_int[i] = AddLiveIn(MF, args_int[i], getRegClassFor(MVT::i64));
       SDOperand argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[i], MVT::i64);
       int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
       if (i == 0) VarArgsBase = FI;
@@ -207,7 +207,7 @@
                                SDFI, DAG.getSrcValue(NULL)));
 
       if (!(added_fp & (1 << i)))
-        MF.addLiveIn(args_float[i]);
+        args_float[i] = AddLiveIn(MF, args_float[i], getRegClassFor(MVT::f64));
       argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[i], MVT::f64);
       FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
       SDFI = DAG.getFrameIndex(FI, MVT::i64);


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.167 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.168
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.167	Fri Sep  2 13:46:02 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Sun Sep  4 01:12:19 2005
@@ -1733,6 +1733,11 @@
       BuildMI(BB, Opc, 1, Result).addReg(Alpha::F31).addReg(Tmp2);
       return Result;
     }
+
+  case ISD::AssertSext:
+  case ISD::AssertZext:
+    return SelectExpr(N.getOperand(0));
+
   }
 
   return 0;