[llvm-commits] CVS: llvm/utils/TableGen/DAGISelEmitter.h TableGen.cpp

Chris Lattner lattner at cs.uiuc.edu
Fri Sep 2 18:14:14 PDT 2005



Changes in directory llvm/utils/TableGen:

DAGISelEmitter.h added (r1.1)
TableGen.cpp updated: 1.38 -> 1.39
---
Log message:

Add an option and stuff implementation of a dag isel emitter


---
Diffs of the changes:  (+45 -0)

 DAGISelEmitter.h |   38 ++++++++++++++++++++++++++++++++++++++
 TableGen.cpp     |    7 +++++++
 2 files changed, 45 insertions(+)


Index: llvm/utils/TableGen/DAGISelEmitter.h
diff -c /dev/null llvm/utils/TableGen/DAGISelEmitter.h:1.1
*** /dev/null	Fri Sep  2 20:14:13 2005
--- llvm/utils/TableGen/DAGISelEmitter.h	Fri Sep  2 20:14:03 2005
***************
*** 0 ****
--- 1,38 ----
+ //===- DAGISelEmitter.h - Generate an instruction selector ------*- C++ -*-===//
+ //
+ //                     The LLVM Compiler Infrastructure
+ //
+ // This file was developed by Chris Lattner and is distributed under
+ // the University of Illinois Open Source License. See LICENSE.TXT for details.
+ //
+ //===----------------------------------------------------------------------===//
+ //
+ // This tablegen backend emits a DAG instruction selector.
+ //
+ //===----------------------------------------------------------------------===//
+ 
+ #ifndef DAGISEL_EMITTER_H
+ #define DAGISEL_EMITTER_H
+ 
+ #include "TableGenBackend.h"
+ #include "CodeGenTarget.h"
+ 
+ namespace llvm {
+ 
+ /// InstrSelectorEmitter - The top-level class which coordinates construction
+ /// and emission of the instruction selector.
+ ///
+ class DAGISelEmitter : public TableGenBackend {
+   RecordKeeper &Records;
+   CodeGenTarget Target;
+ 
+ public:
+   DAGISelEmitter(RecordKeeper &R) : Records(R) {}
+ 
+   // run - Output the isel, returning true on failure.
+   void run(std::ostream &OS) {}
+ };
+ 
+ } // End llvm namespace
+ 
+ #endif


Index: llvm/utils/TableGen/TableGen.cpp
diff -u llvm/utils/TableGen/TableGen.cpp:1.38 llvm/utils/TableGen/TableGen.cpp:1.39
--- llvm/utils/TableGen/TableGen.cpp:1.38	Thu Apr 21 23:13:13 2005
+++ llvm/utils/TableGen/TableGen.cpp	Fri Sep  2 20:14:03 2005
@@ -24,6 +24,7 @@
 #include "InstrInfoEmitter.h"
 #include "AsmWriterEmitter.h"
 #include "InstrSelectorEmitter.h"
+#include "DAGISelEmitter.h"
 #include <algorithm>
 #include <cstdio>
 #include <fstream>
@@ -34,6 +35,7 @@
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenInstrSelector,
+  GenDAGISel,
   PrintEnums,
   Parse
 };
@@ -59,6 +61,8 @@
                                "Generate assembly writer"),
                     clEnumValN(GenInstrSelector, "gen-instr-selector",
                                "Generate an instruction selector"),
+                    clEnumValN(GenDAGISel, "gen-dag-isel",
+                               "Generate a DAG instruction selector"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValN(Parse, "parse",
@@ -465,6 +469,9 @@
     case GenInstrSelector:
       InstrSelectorEmitter(Records).run(*Out);
       break;
+    case GenDAGISel:
+      DAGISelEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
     {
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);






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