[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp PPC32ISelLowering.cpp PPC32ISelLowering.h PPC32ISelPattern.cpp
Chris Lattner
lattner at cs.uiuc.edu
Fri Aug 26 13:25:14 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelDAGToDAG.cpp updated: 1.43 -> 1.44
PPC32ISelLowering.cpp updated: 1.9 -> 1.10
PPC32ISelLowering.h updated: 1.2 -> 1.3
PPC32ISelPattern.cpp updated: 1.171 -> 1.172
---
Log message:
Make fsel emission work with both the pattern and dag-dag selectors, by
giving it a non-instruction opcode. The dag->dag selector used to not
select the operands of the fsel, because it thought that whole tree was
already selected.
---
Diffs of the changes: (+34 -14)
PPC32ISelDAGToDAG.cpp | 9 ++++++++-
PPC32ISelLowering.cpp | 22 +++++++++++-----------
PPC32ISelLowering.h | 15 ++++++++++++++-
PPC32ISelPattern.cpp | 2 +-
4 files changed, 34 insertions(+), 14 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.43 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.44
--- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.43 Fri Aug 26 13:46:49 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp Fri Aug 26 15:25:03 2005
@@ -629,7 +629,8 @@
// target-specific node if it hasn't already been changed.
SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
- if (N->getOpcode() >= ISD::BUILTIN_OP_END)
+ if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
+ N->getOpcode() < PPCISD::FIRST_NUMBER)
return Op; // Already selected.
switch (N->getOpcode()) {
@@ -747,6 +748,12 @@
assert(N->getValueType(0) == MVT::i32);
CurDAG->SelectNodeTo(N, PPC::CNTLZW, MVT::i32, Select(N->getOperand(0)));
break;
+ case PPCISD::FSEL:
+ CurDAG->SelectNodeTo(N, PPC::FSEL, N->getValueType(0),
+ Select(N->getOperand(0)),
+ Select(N->getOperand(1)),
+ Select(N->getOperand(2)));
+ break;
case ISD::ADD: {
MVT::ValueType Ty = N->getValueType(0);
if (Ty == MVT::i32) {
Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.9 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.10
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.9 Fri Aug 26 12:36:52 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp Fri Aug 26 15:25:03 2005
@@ -125,34 +125,34 @@
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETUGE:
case ISD::SETGE:
- return DAG.getTargetNode(PPC::FSEL, ResVT, LHS, TV, FV);
+ return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
case ISD::SETULE:
case ISD::SETLE:
- return DAG.getTargetNode(PPC::FSEL, ResVT,
- DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
+ return DAG.getNode(PPCISD::FSEL, ResVT,
+ DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
}
switch (CC) {
default: assert(0 && "Invalid FSEL condition"); abort();
case ISD::SETULT:
case ISD::SETLT:
- return DAG.getTargetNode(PPC::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV,TV);
+ return DAG.getNode(PPCISD::FSEL, ResVT,
+ DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
case ISD::SETUGE:
case ISD::SETGE:
- return DAG.getTargetNode(PPC::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV,FV);
+ return DAG.getNode(PPCISD::FSEL, ResVT,
+ DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
case ISD::SETUGT:
case ISD::SETGT:
- return DAG.getTargetNode(PPC::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV,TV);
+ return DAG.getNode(PPCISD::FSEL, ResVT,
+ DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
case ISD::SETULE:
case ISD::SETLE:
- return DAG.getTargetNode(PPC::FSEL, ResVT,
- DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV,FV);
+ return DAG.getNode(PPCISD::FSEL, ResVT,
+ DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
}
}
break;
Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.h
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.h:1.2 llvm/lib/Target/PowerPC/PPC32ISelLowering.h:1.3
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.h:1.2 Thu Aug 25 19:52:45 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.h Fri Aug 26 15:25:03 2005
@@ -1,4 +1,4 @@
-//===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Impl. --------*- C++ -*-===//
+//===-- PPC32ISelLowering.h - PPC32 DAG Lowering Interface ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@@ -16,8 +16,21 @@
#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
#include "llvm/Target/TargetLowering.h"
+#include "llvm/CodeGen/SelectionDAG.h"
+#include "PowerPC.h"
namespace llvm {
+ namespace PPCISD {
+ enum NodeType {
+ // Start the numbering where the builting ops and target ops leave off.
+ FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
+
+ /// FSEL - Traditional three-operand fsel node.
+ ///
+ FSEL,
+ };
+ }
+
class PPC32TargetLowering : public TargetLowering {
int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.171 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.172
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.171 Fri Aug 26 12:45:06 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Fri Aug 26 15:25:03 2005
@@ -811,7 +811,7 @@
default:
Node->dump(); std::cerr << '\n';
assert(0 && "Node not handled!\n");
- case ISD::BUILTIN_OP_END+PPC::FSEL:
+ case PPCISD::FSEL:
Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
Tmp3 = SelectExpr(N.getOperand(2));
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