[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.159 -> 1.160
---
Log message:

teach selection dag mask tracking about the fact that select_cc operates like
select.  Also teach it that the bit count instructions can only set the low bits
of the result, depending on the size of the input.

This allows us to compile this:

int %eq0(int %a) {
        %tmp.1 = seteq int %a, 0                ; <bool> [#uses=1]
        %tmp.2 = cast bool %tmp.1 to int                ; <int> [#uses=1]
        ret int %tmp.2
}

To this:

_eq0:
        cntlzw r2, r3
        srwi r3, r2, 5
        blr

instead of this:

_eq0:
        cntlzw r2, r3
        rlwinm r3, r2, 27, 31, 31
        blr

when setcc is marked illegal on ppc (which restores parity to non-illegal 
setcc).  Thanks to Nate for pointing this out.



---
Diffs of the changes:  (+10 -1)

 SelectionDAG.cpp |   11 ++++++++++-
 1 files changed, 10 insertions(+), 1 deletion(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.159 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.160
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.159	Tue Aug 23 23:57:57 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Wed Aug 24 11:46:55 2005
@@ -1026,7 +1026,9 @@
   case ISD::SELECT:
     return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
            MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
-
+  case ISD::SELECT_CC:
+    return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
+           MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
   case ISD::SRL:
     // (ushr X, C1) & C2 == 0   iff  X & (C2 << C1) == 0
     if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
@@ -1043,6 +1045,13 @@
       return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
     }
     return false;
+  case ISD::CTTZ:
+  case ISD::CTLZ:
+  case ISD::CTPOP:
+    // Bit counting instructions can not set the high bits of the result
+    // register.  The max number of bits sets depends on the input.
+    return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
+    
     // TODO we could handle some SRA cases here.
   default: break;
   }