[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

Chris Lattner lattner at cs.uiuc.edu
Mon Aug 22 10:28:42 PDT 2005



Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAGISel.cpp updated: 1.72 -> 1.73
---
Log message:

Fix a problem where constant expr shifts would not have their shift amount
promoted to the right type.  This fixes: IA64/2005-08-22-LegalizerCrash.ll


---
Diffs of the changes:  (+5 -5)

 SelectionDAGISel.cpp |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.72 llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.73
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:1.72	Thu Aug 18 12:35:14 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp	Mon Aug 22 12:28:31 2005
@@ -337,7 +337,7 @@
   void visitUnwind(UnwindInst &I) { assert(0 && "TODO"); }
 
   //
-  void visitBinary(User &I, unsigned Opcode);
+  void visitBinary(User &I, unsigned Opcode, bool isShift = false);
   void visitAdd(User &I) { visitBinary(I, ISD::ADD); }
   void visitSub(User &I);
   void visitMul(User &I) { visitBinary(I, ISD::MUL); }
@@ -350,9 +350,9 @@
   void visitAnd(User &I) { visitBinary(I, ISD::AND); }
   void visitOr (User &I) { visitBinary(I, ISD::OR); }
   void visitXor(User &I) { visitBinary(I, ISD::XOR); }
-  void visitShl(User &I) { visitBinary(I, ISD::SHL); }
+  void visitShl(User &I) { visitBinary(I, ISD::SHL, true); }
   void visitShr(User &I) {
-    visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA);
+    visitBinary(I, I.getType()->isUnsigned() ? ISD::SRL : ISD::SRA, true);
   }
 
   void visitSetCC(User &I, ISD::CondCode SignedOpc, ISD::CondCode UnsignedOpc);
@@ -486,11 +486,11 @@
   visitBinary(I, ISD::SUB);
 }
 
-void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode) {
+void SelectionDAGLowering::visitBinary(User &I, unsigned Opcode, bool isShift) {
   SDOperand Op1 = getValue(I.getOperand(0));
   SDOperand Op2 = getValue(I.getOperand(1));
 
-  if (isa<ShiftInst>(I))
+  if (isShift)
     Op2 = DAG.getNode(ISD::ZERO_EXTEND, TLI.getShiftAmountTy(), Op2);
 
   setValue(&I, DAG.getNode(Opcode, Op1.getValueType(), Op1, Op2));






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