[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

ScheduleDAG.cpp updated: 1.6 -> 1.7
---
Log message:

Implement CopyFromReg, TokenFactor, and fix a bug in CopyToReg.  This allows
us to compile stuff like this:

double %test(double %A, double %B, double %C, double %E) {
        %F = mul double %A, %A
        %G = add double %F, %B
        %H = sub double -0.0, %G
        %I = mul double %H, %C
        %J = add double %I, %E
        ret double %J
}

to:

_test:
        fnmadd f0, f1, f1, f2
        fmadd f1, f0, f3, f4
        blr

woot!



---
Diffs of the changes:  (+30 -0)

 ScheduleDAG.cpp |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6 llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.7
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp:1.6	Fri Aug 19 15:50:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp	Fri Aug 19 16:43:53 2005
@@ -131,13 +131,43 @@
       Op.Val->dump(); 
       assert(0 && "This target-independent node should have been selected!");
     case ISD::EntryToken: break;
+    case ISD::TokenFactor:
+      for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i)
+        Emit(Op.getOperand(i));
+      break;
     case ISD::CopyToReg: {
+      Emit(Op.getOperand(0));   // Emit the chain.
       unsigned Val = Emit(Op.getOperand(2));
       MRI.copyRegToReg(*BB, BB->end(),
                        cast<RegisterSDNode>(Op.getOperand(1))->getReg(), Val,
                        RegMap->getRegClass(Val));
       break;
     }
+    case ISD::CopyFromReg: {
+      Emit(Op.getOperand(0));   // Emit the chain.
+      unsigned SrcReg = cast<RegisterSDNode>(Op.getOperand(1))->getReg();
+      
+      // Figure out the register class to create for the destreg.
+      const TargetRegisterClass *TRC;
+      if (MRegisterInfo::isVirtualRegister(SrcReg)) {
+        TRC = RegMap->getRegClass(SrcReg);
+      } else {
+        // FIXME: we don't know what register class to generate this for.  Do
+        // a brute force search and pick the first match. :(
+        for (MRegisterInfo::regclass_iterator I = MRI.regclass_begin(),
+               E = MRI.regclass_end(); I != E; ++I)
+          if ((*I)->contains(SrcReg)) {
+            TRC = *I;
+            break;
+          }
+        assert(TRC && "Couldn't find register class for reg copy!");
+      }
+      
+      // Create the reg, emit the copy.
+      ResultReg = RegMap->createVirtualRegister(TRC);
+      MRI.copyRegToReg(*BB, BB->end(), ResultReg, SrcReg, TRC);
+      break;
+    }
     }
   }