[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
Nate Begeman
natebegeman at mac.com
Thu Aug 18 20:42:43 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.155 -> 1.156
---
Log message:
Fix a bug where we were passing the wrong number of arguments to an
instruction.
---
Diffs of the changes: (+4 -1)
PPC32ISelPattern.cpp | 5 ++++-
1 files changed, 4 insertions(+), 1 deletion(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.155 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.156
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.155 Thu Aug 18 18:24:50 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Thu Aug 18 22:42:28 2005
@@ -469,7 +469,10 @@
BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
bool GPOpt =
TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor();
- BuildMI(BB, GPOpt ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
+ if (GPOpt)
+ BuildMI(BB, PPC::MFOCRF, 1, IntCR).addReg(PPC::CR7);
+ else
+ BuildMI(BB, PPC::MFCR, 0, IntCR);
if (Inv) {
unsigned Tmp1 = MakeIntReg();
BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
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