[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp PPC32ISelPattern.cpp

[Chris Lattner]

I emailed Jim about this before, but won't this miscompile 65535 -> -1?

-Chris

On Thu, 18 Aug 2005, Nate Begeman wrote:

>
>
> Changes in directory llvm/lib/Target/PowerPC:
>
> PPC32ISelDAGToDAG.cpp updated: 1.8 -> 1.9
> PPC32ISelPattern.cpp updated: 1.151 -> 1.152
> ---
> Log message:
>
> Improve ISD::Constant codegen.
> Now for int foo() { return -1; } we generate:
> _foo:
>        li r3, -1
>        blr
>
> instead of
> _foo:
>        lis r2, -1
>        ori r3, r2, 65535
>        blr
>
>
> ---
> Diffs of the changes:  (+12 -8)
>
> PPC32ISelDAGToDAG.cpp |   18 +++++++++++-------
> PPC32ISelPattern.cpp  |    2 +-
> 2 files changed, 12 insertions(+), 8 deletions(-)
>
>
> Index: llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp
> diff -u llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8 llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.9
> --- llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp:1.8	Thu Aug 18 02:30:46 2005
> +++ llvm/lib/Target/PowerPC/PPC32ISelDAGToDAG.cpp	Thu Aug 18 13:01:39 2005
> @@ -277,15 +277,18 @@
>   case ISD::Constant: {
>     assert(N->getValueType(0) == MVT::i32);
>     unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
> -    if ((unsigned)(short)v == v) {
> +    unsigned Hi = HA16(v);
> +    unsigned Lo = Lo16(v);
> +    if (Hi && Lo) {
> +      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
> +                                            getI32Imm(v >> 16));
> +      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
> +    } else if (Lo) {
>       CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
> -      break;
>     } else {
> -      SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
> -                                            getI32Imm(unsigned(v) >> 16));
> -      CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
> -      break;
> +      CurDAG->SelectNodeTo(N, MVT::i32, PPC::LIS, getI32Imm(v >> 16));
>     }
> +    break;
>   }
>   case ISD::SIGN_EXTEND_INREG:
>     switch(cast<VTSDNode>(N->getOperand(1))->getVT()) {
> @@ -412,12 +415,13 @@
>                          Select(N->getOperand(1)));
>     break;
>   case ISD::AND: {
> -    unsigned Imm, SH, MB, ME;
> +    unsigned Imm;
>     // If this is an and of a value rotated between 0 and 31 bits and then and'd
>     // with a mask, emit rlwinm
>     if (isIntImmediate(N->getOperand(1), Imm) && (isShiftedMask_32(Imm) ||
>                                                   isShiftedMask_32(~Imm))) {
>       SDOperand Val;
> +      unsigned SH, MB, ME;
>       if (isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
>         Val = Select(N->getOperand(0).getOperand(0));
>       } else {
>
>
> Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
> diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.152
> --- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.151	Thu Aug 18 12:16:52 2005
> +++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Thu Aug 18 13:01:39 2005
> @@ -1736,7 +1736,7 @@
>     assert(N.getValueType() == MVT::i32 &&
>            "Only i32 constants are legal on this target!");
>     int v = (int)cast<ConstantSDNode>(N)->getValue();
> -    unsigned Hi = Hi16(v);
> +    unsigned Hi = HA16(v);
>     unsigned Lo = Lo16(v);
>     if (Hi && Lo) {
>       Tmp1 = MakeIntReg();
>
>
>
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>

-Chris

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