[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.164 -> 1.165
---
Log message:

Fix some bugs in the alpha backend, some of which I introduced yesterday,
and some that were preexisting.  All alpha regtests pass now.


---
Diffs of the changes:  (+3 -2)

 AlphaISelPattern.cpp |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.164 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.165
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.164	Tue Aug 16 19:47:24 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Aug 17 12:08:24 2005
@@ -284,6 +284,7 @@
       case MVT::f32:
         args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
         argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
+        DAG.setRoot(argt.getValue(1));
         break;
       case MVT::i1:
       case MVT::i8:
@@ -292,12 +293,12 @@
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count],
                                     getRegClassFor(MVT::i64));
-        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT);
+        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
+        DAG.setRoot(argt.getValue(1));
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
       }
-      DAG.setRoot(argt.getValue(1));
     } else { //more args
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(8, 8 * (count - 6));