[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp PPC32ISelPattern.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelLowering.cpp updated: 1.1 -> 1.2
PPC32ISelPattern.cpp updated: 1.142 -> 1.143
---
Log message:

Implement BR_CC and BRTWOWAY_CC.  This allows the removal of a rather nasty
fixme from the PowerPC backend.  Emit slightly better code for legalizing
select_cc.


---
Diffs of the changes:  (+11 -18)

 PPC32ISelLowering.cpp |    4 ++++
 PPC32ISelPattern.cpp  |   25 +++++++------------------
 2 files changed, 11 insertions(+), 18 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.1 llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.2
--- llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp:1.1	Tue Aug 16 12:14:42 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelLowering.cpp	Tue Aug 16 14:49:35 2005
@@ -66,6 +66,10 @@
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
   setOperationAction(ISD::SELECT, MVT::f64, Expand);
+
+  // PowerPC does not have BRCOND* which requires SetCC
+  setOperationAction(ISD::BRCOND,       MVT::Other, Expand);
+  setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
   
   // PowerPC does not have FP_TO_UINT
   setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.142 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.143
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.142	Tue Aug 16 12:14:42 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Tue Aug 16 14:49:35 2005
@@ -713,22 +713,11 @@
 void ISel::SelectBranchCC(SDOperand N)
 {
   MachineBasicBlock *Dest =
-    cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
+    cast<BasicBlockSDNode>(N.getOperand(4))->getBasicBlock();
 
   Select(N.getOperand(0));  //chain
-  
-  // FIXME: Until we have Branch_CC and Branch_Twoway_CC, we're going to have to
-  // Fake it up by hand by checking to see if op 1 is a SetCC, or a boolean.
-  unsigned CCReg;
-  ISD::CondCode CC;
-  SDOperand Cond = N.getOperand(1);
-  if (Cond.getOpcode() == ISD::SETCC) {
-    CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
-    CCReg = SelectCC(Cond.getOperand(0), Cond.getOperand(1), CC);
-  } else {
-    CC = ISD::SETNE;
-    CCReg = SelectCC(Cond, ISelDAG->getConstant(0, Cond.getValueType()), CC);
-  }
+  ISD::CondCode CC = cast<CondCodeSDNode>(N.getOperand(1))->get();
+  unsigned CCReg = SelectCC(N.getOperand(2), N.getOperand(3), CC);
   unsigned Opc = getBCCForSetCC(CC);
 
   // Iterate to the next basic block
@@ -739,9 +728,9 @@
   // and build a PowerPC branch pseudo-op, suitable for long branch conversion
   // if necessary by the branch selection pass.  Otherwise, emit a standard
   // conditional branch.
-  if (N.getOpcode() == ISD::BRCONDTWOWAY) {
+  if (N.getOpcode() == ISD::BRTWOWAY_CC) {
     MachineBasicBlock *Fallthrough =
-      cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
+      cast<BasicBlockSDNode>(N.getOperand(5))->getBasicBlock();
     if (Dest != It) {
       BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
         .addMBB(Dest).addMBB(Fallthrough);
@@ -1882,8 +1871,8 @@
     BuildMI(BB, PPC::B, 1).addMBB(Dest);
     return;
   }
-  case ISD::BRCOND:
-  case ISD::BRCONDTWOWAY:
+  case ISD::BR_CC:
+  case ISD::BRTWOWAY_CC:
     SelectBranchCC(N);
     return;
   case ISD::CopyToReg: