[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.128 -> 1.129
---
Log message:

add a small simplification that can be exposed after promotion/expansion


---
Diffs of the changes:  (+7 -2)

 SelectionDAG.cpp |    9 +++++++--
 1 files changed, 7 insertions(+), 2 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.128 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.129
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.128	Fri Aug  5 11:55:31 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sun Aug  7 00:00:44 2005
@@ -770,8 +770,6 @@
 
   // If we know the result of a setcc has the top bits zero, use this info.
   switch (Op.getOpcode()) {
-  case ISD::UNDEF:
-    return true;
   case ISD::Constant:
     return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
 
@@ -1044,6 +1042,13 @@
           MVT::getSizeInBits(cast<VTSDNode>(N1.getOperand(1))->getVT());
         if ((C2 & (~0ULL << ExtendBits)) == 0)
           return getNode(ISD::AND, VT, N1.getOperand(0), N2);
+      } else if (N1.getOpcode() == ISD::OR) {
+        if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
+          if ((ORI->getValue() & C2) == C2) {
+            // If the 'or' is setting all of the bits that we are masking for,
+            // we know the result of the AND will be the AND mask itself.
+            return N2;
+          }
       }
       break;
     case ISD::OR: