[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.126 -> 1.127
---
Log message:

Update to use the new MathExtras.h support for log2 computation.
Patch contributed by Jim Laskey!



---
Diffs of the changes:  (+6 -14)

 SelectionDAG.cpp |   20 ++++++--------------
 1 files changed, 6 insertions(+), 14 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.126 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.127
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.126	Wed Jul 27 01:12:33 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Tue Aug  2 14:26:06 2005
@@ -16,6 +16,7 @@
 #include "llvm/GlobalValue.h"
 #include "llvm/Assembly/Writer.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetLowering.h"
 #include <iostream>
 #include <set>
@@ -45,15 +46,6 @@
   }
 }
 
-static unsigned ExactLog2(uint64_t Val) {
-  unsigned Count = 0;
-  while (Val != 1) {
-    Val >>= 1;
-    ++Count;
-  }
-  return Count;
-}
-
 // isInvertibleForFree - Return true if there is no cost to emitting the logical
 // inverse of this node.
 static bool isInvertibleForFree(SDOperand N) {
@@ -527,7 +519,7 @@
             // Perform the xform if the AND RHS is a single bit.
             if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
               return getNode(ISD::SRL, VT, N1,
-                             getConstant(ExactLog2(AndRHS->getValue()),
+                             getConstant(Log2_64(AndRHS->getValue()),
                                                    TLI.getShiftAmountTy()));
             }
           } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) {
@@ -535,7 +527,7 @@
             // Perform the xform if C2 is a single bit.
             if ((C2 & (C2-1)) == 0) {
               return getNode(ISD::SRL, VT, N1,
-                             getConstant(ExactLog2(C2),TLI.getShiftAmountTy()));
+                             getConstant(Log2_64(C2),TLI.getShiftAmountTy()));
             }
           }
         }
@@ -956,7 +948,7 @@
 
       // FIXME: Move this to the DAG combiner when it exists.
       if ((C2 & C2-1) == 0) {
-        SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy());
+        SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy());
         return getNode(ISD::SHL, VT, N1, ShAmt);
       }
       break;
@@ -974,7 +966,7 @@
     case ISD::UDIV:
       // FIXME: Move this to the DAG combiner when it exists.
       if ((C2 & C2-1) == 0 && C2) {
-        SDOperand ShAmt = getConstant(ExactLog2(C2), TLI.getShiftAmountTy());
+        SDOperand ShAmt = getConstant(Log2_64(C2), TLI.getShiftAmountTy());
         return getNode(ISD::SRL, VT, N1, ShAmt);
       }
       break;
@@ -1410,7 +1402,7 @@
               // exists.
               if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2))
                 if ((AC->getValue() & (AC->getValue()-1)) == 0) {
-                  unsigned ShCtV = ExactLog2(AC->getValue());
+                  unsigned ShCtV = Log2_64(AC->getValue());
                   ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
                   SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy());
                   SDOperand Shift = getNode(ISD::SRL, XType,