[llvm-commits] CVS: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/SparcV9:

SparcV9BurgISel.cpp updated: 1.24 -> 1.25
---
Log message:

Update to use the new MathExtras.h support for log2 computation.
Patch contributed by Jim Laskey!



---
Diffs of the changes:  (+5 -5)

 SparcV9BurgISel.cpp |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.24 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.25
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.24	Wed Jul 27 01:12:33 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp	Tue Aug  2 14:25:03 2005
@@ -2306,7 +2306,6 @@
                                                    constOp->getType(),
                                                    isValidConst);
     if (isValidConst) {
-      unsigned pow;
       bool needNeg = false;
       if (C < 0) {
         needNeg = true;
@@ -2323,7 +2322,8 @@
         else
           M = BuildMI(V9::ADDr,3).addReg(lval).addMReg(Zero).addRegDef(destVal);
         mvec.push_back(M);
-      } else if (isPowerOf2(C, pow)) {
+      } else if (isPowerOf2_64(C)) {
+        unsigned pow = Log2_64(C);
         if(!needNeg) {
         unsigned opSize = target.getTargetData().getTypeSize(resultType);
         MachineOpCode opCode = (opSize <= 32)? V9::SLLr5 : V9::SLLXr6;
@@ -2464,7 +2464,6 @@
   const Type* resultType = instrNode->getInstruction()->getType();
 
   if (resultType->isInteger()) {
-    unsigned pow;
     bool isValidConst;
     int64_t C = (int64_t) ConvertConstantToIntType(target, constOp,
                                                    constOp->getType(),
@@ -2479,7 +2478,8 @@
       if (C == 1) {
         mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addMReg(ZeroReg)
                        .addRegDef(destVal));
-      } else if (isPowerOf2(C, pow)) {
+      } else if (isPowerOf2_64(C)) {
+        unsigned pow = Log2_64(C);
         unsigned opCode;
         Value* shiftOperand;
         unsigned opSize = target.getTargetData().getTypeSize(resultType);
@@ -2539,7 +2539,7 @@
                        .addRegDef(destVal));
       }
 
-      if (needNeg && (C == 1 || isPowerOf2(C, pow))) {
+      if (needNeg && (C == 1 || isPowerOf2_64(C))) {
         // insert <reg = SUB 0, reg> after the instr to flip the sign
         mvec.push_back(CreateIntNegInstruction(target, destVal));
       }