[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC32RegisterInfo.cpp
Nate Begeman
natebegeman at mac.com
Wed Jul 27 16:11:38 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.105 -> 1.106
PPC32RegisterInfo.cpp updated: 1.13 -> 1.14
---
Log message:
Fix some comments
---
Diffs of the changes: (+2 -4)
PPC32ISelPattern.cpp | 4 +---
PPC32RegisterInfo.cpp | 2 +-
2 files changed, 2 insertions(+), 4 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.106
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105 Wed Jul 27 01:12:33 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Wed Jul 27 18:11:27 2005
@@ -1656,9 +1656,6 @@
return Result;
case ISD::AND:
- // FIXME: should add check in getImmediateForOpcode to return a value
- // indicating the immediate is a run of set bits so we can emit a bitfield
- // clear with RLWINM instead.
switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
default: assert(0 && "unhandled result code");
case 0: // No immediate
@@ -1690,6 +1687,7 @@
Tmp3 = Tmp2 >> 16; // MB
Tmp2 &= 0xFFFF; // ME
+ // FIXME: Catch SHL-AND in addition to SRL-AND in this block.
if (N.getOperand(0).getOpcode() == ISD::SRL)
if (ConstantSDNode *SA =
dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.13 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.14
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.13 Wed Jul 27 01:06:29 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp Wed Jul 27 18:11:27 2005
@@ -263,7 +263,7 @@
// Update frame info to pretend that this is part of the stack...
MFI->setStackSize(NumBytes);
- // If , adjust stack pointer: r1 -= numbytes.
+ // Adjust stack pointer: r1 -= numbytes.
if (NumBytes <= 32768) {
MI=BuildMI(PPC::STWU,3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
MBB.insert(MBBI, MI);
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