[llvm-commits] CVS: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp X86AsmPrinter.cpp X86ISelPattern.cpp X86ISelSimple.cpp X86PeepholeOpt.cpp X86RegisterInfo.cpp X86Subtarget.cpp X86TargetMachine.cpp
Jeff Cohen
jeffc at jolt-lang.org
Tue Jul 26 23:12:58 PDT 2005
Changes in directory llvm/lib/Target/X86:
X86ATTAsmPrinter.cpp updated: 1.7 -> 1.8
X86AsmPrinter.cpp updated: 1.144 -> 1.145
X86ISelPattern.cpp updated: 1.154 -> 1.155
X86ISelSimple.cpp updated: 1.320 -> 1.321
X86PeepholeOpt.cpp updated: 1.39 -> 1.40
X86RegisterInfo.cpp updated: 1.106 -> 1.107
X86Subtarget.cpp updated: 1.3 -> 1.4
X86TargetMachine.cpp updated: 1.83 -> 1.84
---
Log message:
Eliminate all remaining tabs and trailing spaces.
---
Diffs of the changes: (+72 -72)
X86ATTAsmPrinter.cpp | 2 -
X86AsmPrinter.cpp | 16 ++++-----
X86ISelPattern.cpp | 86 +++++++++++++++++++++++++--------------------------
X86ISelSimple.cpp | 2 -
X86PeepholeOpt.cpp | 22 ++++++-------
X86RegisterInfo.cpp | 8 ++--
X86Subtarget.cpp | 6 +--
X86TargetMachine.cpp | 2 -
8 files changed, 72 insertions(+), 72 deletions(-)
Index: llvm/lib/Target/X86/X86ATTAsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.7 llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.8
--- llvm/lib/Target/X86/X86ATTAsmPrinter.cpp:1.7 Thu Jul 14 17:52:25 2005
+++ llvm/lib/Target/X86/X86ATTAsmPrinter.cpp Wed Jul 27 01:12:34 2005
@@ -102,7 +102,7 @@
FnStubs.insert(Name);
O << "L" << Name << "$stub";
} else if (GV->hasLinkOnceLinkage()) {
- // Link-once, External, or Weakly-linked global variables need
+ // Link-once, External, or Weakly-linked global variables need
// non-lazily-resolved stubs
LinkOnceStubs.insert(Name);
O << "L" << Name << "$non_lazy_ptr";
Index: llvm/lib/Target/X86/X86AsmPrinter.cpp
diff -u llvm/lib/Target/X86/X86AsmPrinter.cpp:1.144 llvm/lib/Target/X86/X86AsmPrinter.cpp:1.145
--- llvm/lib/Target/X86/X86AsmPrinter.cpp:1.144 Fri Jul 15 20:59:47 2005
+++ llvm/lib/Target/X86/X86AsmPrinter.cpp Wed Jul 27 01:12:34 2005
@@ -25,7 +25,7 @@
using namespace llvm;
using namespace x86;
-Statistic<> llvm::x86::EmittedInsts("asm-printer",
+Statistic<> llvm::x86::EmittedInsts("asm-printer",
"Number of machine instrs printed");
enum AsmWriterFlavorTy { att, intel };
@@ -58,7 +58,7 @@
leadingUnderscore = false;
#endif
}
-
+
if (leadingUnderscore || forCygwin || forDarwin)
GlobalPrefix = "_";
@@ -67,7 +67,7 @@
Data64bitsDirective = 0; // we can't emit a 64-bit unit
ZeroDirective = "\t.space\t"; // ".space N" emits N zeros.
}
-
+
return AsmPrinter::doInitialization(M);
}
@@ -107,7 +107,7 @@
Constant *C = I->getInitializer();
unsigned Size = TD.getTypeSize(C->getType());
unsigned Align = TD.getTypeAlignmentShift(C->getType());
-
+
if (C->isNullValue() &&
(I->hasLinkOnceLinkage() || I->hasInternalLinkage() ||
I->hasWeakLinkage() /* FIXME: Verify correct */)) {
@@ -116,7 +116,7 @@
O << "\t.local " << name << "\n";
if (forDarwin && I->hasInternalLinkage())
O << "\t.lcomm " << name << "," << Size << "," << Align;
- else
+ else
O << "\t.comm " << name << "," << Size;
if (!forCygwin && !forDarwin)
O << "," << (1 << Align);
@@ -147,7 +147,7 @@
SwitchSection(O, CurSection, ".data");
break;
}
-
+
emitAlignment(Align);
if (!forCygwin && !forDarwin) {
O << "\t.type " << name << ", at object\n";
@@ -161,7 +161,7 @@
emitGlobalConstant(C);
}
}
-
+
if (forDarwin) {
// Output stubs for external global variables
if (GVStubs.begin() != GVStubs.end())
@@ -191,7 +191,7 @@
}
O << "\n";
-
+
// Output stubs for link-once variables
if (LinkOnceStubs.begin() != LinkOnceStubs.end())
O << ".data\n.align 2\n";
Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.154 llvm/lib/Target/X86/X86ISelPattern.cpp:1.155
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.154 Mon Jul 18 23:52:44 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp Wed Jul 27 01:12:34 2005
@@ -105,7 +105,7 @@
addRegisterClass(MVT::i8, X86::R8RegisterClass);
addRegisterClass(MVT::i16, X86::R16RegisterClass);
addRegisterClass(MVT::i32, X86::R32RegisterClass);
-
+
// Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
// operation.
setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
@@ -117,10 +117,10 @@
// this operation.
setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
-
+
// We can handle SINT_TO_FP from i64 even though i64 isn't legal.
setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
-
+
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
@@ -137,7 +137,7 @@
setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
-
+
setOperationAction(ISD::READIO , MVT::i1 , Expand);
setOperationAction(ISD::READIO , MVT::i8 , Expand);
setOperationAction(ISD::READIO , MVT::i16 , Expand);
@@ -146,16 +146,16 @@
setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
-
+
// These should be promoted to a larger select which is supported.
setOperationAction(ISD::SELECT , MVT::i1 , Promote);
setOperationAction(ISD::SELECT , MVT::i8 , Promote);
-
+
if (X86ScalarSSE) {
// Set up the FP register classes.
addRegisterClass(MVT::f32, X86::RXMMRegisterClass);
addRegisterClass(MVT::f64, X86::RXMMRegisterClass);
-
+
// SSE has no load+extend ops
setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
@@ -177,12 +177,12 @@
} else {
// Set up the FP register classes.
addRegisterClass(MVT::f64, X86::RFPRegisterClass);
-
+
if (!UnsafeFPMath) {
setOperationAction(ISD::FSIN , MVT::f64 , Expand);
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
}
-
+
addLegalFPImmediate(+0.0); // FLD0
addLegalFPImmediate(+1.0); // FLD1
addLegalFPImmediate(-0.0); // FLD0/FCHS
@@ -195,7 +195,7 @@
maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
allowUnalignedStores = true; // x86 supports it!
}
-
+
// Return the number of bytes that a function should pop when it returns (in
// addition to the space used by the return address).
//
@@ -217,7 +217,7 @@
/// LowerCallTo - This hook lowers an abstract call to a function into an
/// actual call.
virtual std::pair<SDOperand, SDOperand>
- LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
+ LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
bool isTailCall, SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG);
@@ -226,7 +226,7 @@
virtual std::pair<SDOperand,SDOperand>
LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
const Type *ArgTy, SelectionDAG &DAG);
-
+
virtual std::pair<SDOperand, SDOperand>
LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
SelectionDAG &DAG);
@@ -240,7 +240,7 @@
LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
bool isTailCall,
SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
-
+
// Fast Calling Convention implementation.
std::vector<SDOperand> LowerFastCCArguments(Function &F, SelectionDAG &DAG);
std::pair<SDOperand, SDOperand>
@@ -259,7 +259,7 @@
std::pair<SDOperand, SDOperand>
X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
bool isVarArg, unsigned CallingConv,
- bool isTailCall,
+ bool isTailCall,
SDOperand Callee, ArgListTy &Args,
SelectionDAG &DAG) {
assert((!isVarArg || CallingConv == CallingConv::C) &&
@@ -579,7 +579,7 @@
unsigned ArgIncrement = 4;
unsigned ObjSize = 0;
SDOperand ArgValue;
-
+
switch (ObjectVT) {
default: assert(0 && "Unhandled argument type!");
case MVT::i1:
@@ -1025,8 +1025,8 @@
/// TheDAG - The DAG being selected during Select* operations.
SelectionDAG *TheDAG;
-
- /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
+
+ /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
/// make the right decision when generating code for different targets.
const X86Subtarget *Subtarget;
public:
@@ -1353,7 +1353,7 @@
// the value at address GV, not the value of GV itself. This means that
// the GlobalAddress must be in the base or index register of the address,
// not the GV offset field.
- if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
(GV->hasWeakLinkage() || GV->isExternal())) {
break;
} else {
@@ -1788,7 +1788,7 @@
// There's no SSE equivalent of FCMOVE. In some cases we can fake it up, in
// Others we will have to do the PowerPC thing and generate an MBB for the
// true and false values and select between them with a PHI.
- if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
+ if (X86ScalarSSE && (SVT == MVT::f32 || SVT == MVT::f64)) {
if (0 && CondCode != NOT_SET) {
// FIXME: check for min and max
} else {
@@ -1846,7 +1846,7 @@
case MVT::f64: Opc = CMOVTABFP[CondCode]; break;
}
}
-
+
// Finally, if we weren't able to fold this, just emit the condition and test
// it.
if (CondCode == NOT_SET || Opc == 0) {
@@ -2186,12 +2186,12 @@
Node->dump();
assert(0 && "Node not handled!\n");
case ISD::FP_EXTEND:
- assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
+ assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, X86::CVTSS2SDrr, 1, Result).addReg(Tmp1);
return Result;
case ISD::FP_ROUND:
- assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
+ assert(X86ScalarSSE && "Scalar SSE FP must be enabled to use f32");
Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, X86::CVTSD2SSrr, 1, Result).addReg(Tmp1);
return Result;
@@ -2216,7 +2216,7 @@
BuildMI(BB, X86::MOV32rr, 1,
Result).addReg(cast<RegSDNode>(Node)->getReg());
return Result;
- }
+ }
case ISD::FrameIndex:
Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
@@ -2266,7 +2266,7 @@
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
// For Darwin, external and weak symbols are indirect, so we want to load
// the value at address GV, not the value of GV itself.
- if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
(GV->hasWeakLinkage() || GV->isExternal())) {
BuildMI(BB, X86::MOV32rm, 4, Result).addReg(0).addZImm(1).addReg(0)
.addGlobalAddress(GV, false, 0);
@@ -2383,7 +2383,7 @@
BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
return Result;
}
-
+
ContainsFPCode = true;
// Spill the integer to memory and reload it from there.
@@ -2423,7 +2423,7 @@
abort();
}
return Result;
- }
+ }
// Change the floating point control register to use "round towards zero"
// mode when truncating to an integer value.
@@ -2836,8 +2836,8 @@
case MVT::i32: Opc = 7; break;
case MVT::f32: Opc = 8; break;
// For F64, handle promoted load operations (from F32) as well!
- case MVT::f64:
- assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) &&
+ case MVT::f64:
+ assert((!X86ScalarSSE || Op1.getOpcode() == ISD::LOAD) &&
"SSE load should have been promoted");
Opc = Op1.getOpcode() == ISD::LOAD ? 9 : 8; break;
}
@@ -3273,12 +3273,12 @@
case MVT::i16: Opc = X86::MOV16rm; break;
case MVT::i32: Opc = X86::MOV32rm; break;
case MVT::f32: Opc = X86::MOVSSrm; break;
- case MVT::f64:
+ case MVT::f64:
if (X86ScalarSSE) {
Opc = X86::MOVSDrm;
} else {
Opc = X86::FLD64m;
- ContainsFPCode = true;
+ ContainsFPCode = true;
}
break;
}
@@ -3497,7 +3497,7 @@
unsigned RegOp1 = SelectExpr(N.getOperand(4));
unsigned RegOp2 =
Node->getNumOperands() > 5 ? SelectExpr(N.getOperand(5)) : 0;
-
+
switch (N.getOperand(4).getValueType()) {
default: assert(0 && "Bad thing to pass in regs");
case MVT::i1:
@@ -3595,7 +3595,7 @@
assert(0 && "readport already emitted!?");
} else
Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
-
+
Select(Node->getOperand(0)); // Select the chain.
// If the port is a single-byte constant, use the immediate form.
@@ -3640,7 +3640,7 @@
std::cerr << "Cannot do input on this data type";
exit(1);
}
-
+
}
return 0;
@@ -4066,7 +4066,7 @@
RegOp1 = SelectExpr(TailCallNode->getOperand(4));
if (TailCallNode->getNumOperands() > 5)
RegOp2 = SelectExpr(TailCallNode->getOperand(5));
-
+
switch (TailCallNode->getOperand(4).getValueType()) {
default: assert(0 && "Bad thing to pass in regs");
case MVT::i1:
@@ -4167,12 +4167,12 @@
case MVT::i16: Opc = X86::MOV16rr; break;
case MVT::i32: Opc = X86::MOV32rr; break;
case MVT::f32: Opc = X86::MOVAPSrr; break;
- case MVT::f64:
+ case MVT::f64:
if (X86ScalarSSE) {
Opc = X86::MOVAPDrr;
} else {
- Opc = X86::FpMOV;
- ContainsFPCode = true;
+ Opc = X86::FpMOV;
+ ContainsFPCode = true;
}
break;
}
@@ -4191,8 +4191,8 @@
assert(0 && "Unknown return instruction!");
case 3:
assert(N.getOperand(1).getValueType() == MVT::i32 &&
- N.getOperand(2).getValueType() == MVT::i32 &&
- "Unknown two-register value!");
+ N.getOperand(2).getValueType() == MVT::i32 &&
+ "Unknown two-register value!");
if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
Tmp1 = SelectExpr(N.getOperand(1));
Tmp2 = SelectExpr(N.getOperand(2));
@@ -4224,7 +4224,7 @@
addFrameReference(BuildMI(BB, X86::MOVSSmr, 5), FrameIdx).addReg(Tmp1);
addFrameReference(BuildMI(BB, X86::FLD32m, 4, X86::FP0), FrameIdx);
BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
- ContainsFPCode = true;
+ ContainsFPCode = true;
} else {
assert(0 && "MVT::f32 only legal with scalar sse fp");
abort();
@@ -4239,7 +4239,7 @@
addFrameReference(BuildMI(BB, X86::MOVSDmr, 5), FrameIdx).addReg(Tmp1);
addFrameReference(BuildMI(BB, X86::FLD64m, 4, X86::FP0), FrameIdx);
BuildMI(BB, X86::FpSETRESULT, 1).addReg(X86::FP0);
- ContainsFPCode = true;
+ ContainsFPCode = true;
} else {
BuildMI(BB, X86::FpSETRESULT, 1).addReg(Tmp1);
}
@@ -4367,7 +4367,7 @@
default: assert(0 && "Cannot truncstore this type!");
case MVT::i1: Opc = X86::MOV8mr; break;
case MVT::f32:
- assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs");
+ assert(!X86ScalarSSE && "Cannot truncstore scalar SSE regs");
Opc = X86::FST32m; break;
}
@@ -4426,7 +4426,7 @@
GlobalValue *GV = GA->getGlobal();
// For Darwin, external and weak symbols are indirect, so we want to load
// the value at address GV, not the value of GV itself.
- if (Subtarget->getIndirectExternAndWeakGlobals() &&
+ if (Subtarget->getIndirectExternAndWeakGlobals() &&
(GV->hasWeakLinkage() || GV->isExternal())) {
Tmp1 = MakeReg(MVT::i32);
BuildMI(BB, X86::MOV32rm, 4, Tmp1).addReg(0).addZImm(1).addReg(0)
Index: llvm/lib/Target/X86/X86ISelSimple.cpp
diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.320 llvm/lib/Target/X86/X86ISelSimple.cpp:1.321
--- llvm/lib/Target/X86/X86ISelSimple.cpp:1.320 Sat Jun 18 13:34:52 2005
+++ llvm/lib/Target/X86/X86ISelSimple.cpp Wed Jul 27 01:12:34 2005
@@ -3510,7 +3510,7 @@
unsigned FltAlign = TM.getTargetData().getFloatAlignment();
int FrameIdx = F->getFrameInfo()->CreateStackObject(4, FltAlign);
addFrameReference(BuildMI(*BB, IP, X86::FST32m, 5),
- FrameIdx).addReg(SrcReg);
+ FrameIdx).addReg(SrcReg);
addFrameReference(BuildMI(*BB, IP, X86::FLD32m, 5, DestReg), FrameIdx);
}
} else if (SrcClass == cLong) {
Index: llvm/lib/Target/X86/X86PeepholeOpt.cpp
diff -u llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.39 llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.40
--- llvm/lib/Target/X86/X86PeepholeOpt.cpp:1.39 Thu Apr 21 18:38:14 2005
+++ llvm/lib/Target/X86/X86PeepholeOpt.cpp Wed Jul 27 01:12:34 2005
@@ -30,7 +30,7 @@
virtual bool runOnMachineFunction(MachineFunction &MF);
bool PeepholeOptimize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I);
+ MachineBasicBlock::iterator &I);
virtual const char *getPassName() const { return "X86 Peephole Optimizer"; }
};
@@ -44,17 +44,17 @@
for (MachineFunction::iterator BI = MF.begin(), E = MF.end(); BI != E; ++BI)
for (MachineBasicBlock::iterator I = BI->begin(); I != BI->end(); )
if (PeepholeOptimize(*BI, I)) {
- Changed = true;
+ Changed = true;
++NumPHOpts;
} else
- ++I;
+ ++I;
return Changed;
}
bool PH::PeepholeOptimize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I) {
+ MachineBasicBlock::iterator &I) {
assert(I != MBB.end());
MachineBasicBlock::iterator NextI = next(I);
@@ -218,20 +218,20 @@
if (MI->getOperand(1).isImmediate()) { // avoid mov EAX, <value>
int Val = MI->getOperand(1).getImmedValue();
if (Val == 0) { // mov EAX, 0 -> xor EAX, EAX
- static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr};
- unsigned Reg = MI->getOperand(0).getReg();
- I = MBB.insert(MBB.erase(I),
+ static const unsigned Opcode[] ={X86::XOR8rr,X86::XOR16rr,X86::XOR32rr};
+ unsigned Reg = MI->getOperand(0).getReg();
+ I = MBB.insert(MBB.erase(I),
BuildMI(Opcode[Size], 2, Reg).addReg(Reg).addReg(Reg));
- return true;
+ return true;
} else if (Val == -1) { // mov EAX, -1 -> or EAX, -1
- // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
+ // TODO: 'or Reg, -1' has a smaller encoding than 'mov Reg, -1'
}
}
return false;
#endif
case X86::BSWAP32r: // Change bswap EAX, bswap EAX into nothing
if (Next->getOpcode() == X86::BSWAP32r &&
- MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
+ MI->getOperand(0).getReg() == Next->getOperand(0).getReg()) {
I = MBB.erase(MBB.erase(I));
return true;
}
@@ -314,7 +314,7 @@
virtual bool runOnMachineFunction(MachineFunction &MF);
bool PeepholeOptimize(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator &I);
+ MachineBasicBlock::iterator &I);
virtual const char *getPassName() const {
return "X86 SSA-based Peephole Optimizer";
Index: llvm/lib/Target/X86/X86RegisterInfo.cpp
diff -u llvm/lib/Target/X86/X86RegisterInfo.cpp:1.106 llvm/lib/Target/X86/X86RegisterInfo.cpp:1.107
--- llvm/lib/Target/X86/X86RegisterInfo.cpp:1.106 Wed Jul 6 13:59:04 2005
+++ llvm/lib/Target/X86/X86RegisterInfo.cpp Wed Jul 27 01:12:34 2005
@@ -387,10 +387,10 @@
MachineInstr *New = 0;
if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
- New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
+ New=BuildMI(X86::SUB32ri, 1, X86::ESP, MachineOperand::UseAndDef)
.addZImm(Amount);
} else {
- assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
+ assert(Old->getOpcode() == X86::ADJCALLSTACKUP);
// factor out the amount the callee already popped.
unsigned CalleeAmt = Old->getOperand(1).getImmedValue();
Amount -= CalleeAmt;
@@ -407,7 +407,7 @@
// something off the stack pointer, add it back. We do this until we have
// more advanced stack pointer tracking ability.
if (unsigned CalleeAmt = I->getOperand(1).getImmedValue()) {
- MachineInstr *New =
+ MachineInstr *New =
BuildMI(X86::SUB32ri, 1, X86::ESP,
MachineOperand::UseAndDef).addZImm(CalleeAmt);
MBB.insert(I, New);
@@ -475,7 +475,7 @@
// Save EBP into the appropriate stack slot...
MI = addRegOffset(BuildMI(X86::MOV32mr, 5), // mov [ESP-<offset>], EBP
- X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
+ X86::ESP, EBPOffset+NumBytes).addReg(X86::EBP);
MBB.insert(MBBI, MI);
// Update EBP with the new base value...
Index: llvm/lib/Target/X86/X86Subtarget.cpp
diff -u llvm/lib/Target/X86/X86Subtarget.cpp:1.3 llvm/lib/Target/X86/X86Subtarget.cpp:1.4
--- llvm/lib/Target/X86/X86Subtarget.cpp:1.3 Mon Jul 11 21:41:19 2005
+++ llvm/lib/Target/X86/X86Subtarget.cpp Wed Jul 27 01:12:34 2005
@@ -15,8 +15,8 @@
#include "llvm/Module.h"
using namespace llvm;
-X86Subtarget::X86Subtarget(const Module &M)
- : TargetSubtarget(), stackAlignment(8),
+X86Subtarget::X86Subtarget(const Module &M)
+ : TargetSubtarget(), stackAlignment(8),
indirectExternAndWeakGlobals(false), asmDarwinLinkerStubs(false),
asmLeadingUnderscore(false), asmAlignmentIsInBytes(false),
asmPrintDotLocalConstants(false), asmPrintDotLCommConstants(false),
@@ -25,7 +25,7 @@
bool forCygwin = false;
bool forDarwin = false;
bool forWindows = false;
-
+
// Set the boolean corresponding to the current target triple, or the default
// if one cannot be determined, to true.
const std::string& TT = M.getTargetTriple();
Index: llvm/lib/Target/X86/X86TargetMachine.cpp
diff -u llvm/lib/Target/X86/X86TargetMachine.cpp:1.83 llvm/lib/Target/X86/X86TargetMachine.cpp:1.84
--- llvm/lib/Target/X86/X86TargetMachine.cpp:1.83 Mon Jul 11 20:41:54 2005
+++ llvm/lib/Target/X86/X86TargetMachine.cpp Wed Jul 27 01:12:34 2005
@@ -105,7 +105,7 @@
// does to emit statically compiled machine code.
bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
CodeGenFileType FileType) {
- if (FileType != TargetMachine::AssemblyFile &&
+ if (FileType != TargetMachine::AssemblyFile &&
FileType != TargetMachine::ObjectFile) return true;
// FIXME: Implement efficient support for garbage collection intrinsics.
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