[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp PPC32ISelPattern.cpp PowerPCBranchSelector.cpp PowerPCTargetMachine.cpp

[Jeff Cohen]

Changes in directory llvm/lib/Target/PowerPC:

PPC32CodeEmitter.cpp updated: 1.32 -> 1.33
PPC32ISelPattern.cpp updated: 1.104 -> 1.105
PowerPCBranchSelector.cpp updated: 1.11 -> 1.12
PowerPCTargetMachine.cpp updated: 1.56 -> 1.57
---
Log message:

Eliminate all remaining tabs and trailing spaces.

---
Diffs of the changes:  (+15 -15)

 PPC32CodeEmitter.cpp      |    4 ++--
 PPC32ISelPattern.cpp      |   22 +++++++++++-----------
 PowerPCBranchSelector.cpp |    2 +-
 PowerPCTargetMachine.cpp  |    2 +-
 4 files changed, 15 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.32 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.33
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.32	Thu Jul 21 15:44:42 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp	Wed Jul 27 01:12:33 2005
@@ -201,7 +201,7 @@
       case PPC::LIS:
         if (isExternal)
           Reloc = PPC::reloc_absolute_ptr_high;   // Pointer to stub
-        else 
+        else
           Reloc = PPC::reloc_absolute_high;       // Pointer to symbol
         break;
       case PPC::LA:
@@ -221,7 +221,7 @@
       case PPC::STFD:
         if (isExternal)
           Reloc = PPC::reloc_absolute_ptr_low;
-        else 
+        else
           Reloc = PPC::reloc_absolute_low;
         break;
       }


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.104 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.105
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.104	Mon Jul 25 16:15:28 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Jul 27 01:12:33 2005
@@ -77,7 +77,7 @@
         setOperationAction(ISD::FSQRT, MVT::f64, Expand);
         setOperationAction(ISD::FSQRT, MVT::f32, Expand);
       }
-            
+
       //PowerPC does not have CTPOP or CTTZ
       setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
@@ -103,11 +103,11 @@
 
     virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
                                    Value *VAListV, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand,SDOperand>
       LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
                  const Type *ArgTy, SelectionDAG &DAG);
-    
+
     virtual std::pair<SDOperand, SDOperand>
     LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
                             SelectionDAG &DAG);
@@ -288,7 +288,7 @@
 std::pair<SDOperand, SDOperand>
 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
                                  const Type *RetTy, bool isVarArg,
-                                 unsigned CallingConv, bool isTailCall, 
+                                 unsigned CallingConv, bool isTailCall,
                                  SDOperand Callee, ArgListTy &Args,
                                  SelectionDAG &DAG) {
   // args_to_use will accumulate outgoing args for the ISD::CALL case in
@@ -992,7 +992,7 @@
 bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
   bool IsRotate = false;
   unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
-  
+
   SDOperand Op0 = OR.getOperand(0);
   SDOperand Op1 = OR.getOperand(1);
 
@@ -1046,21 +1046,21 @@
   // constant as its input, make that the inserted value so that we can combine
   // the shift into the rotate part of the rlwimi instruction
   if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
-    if (Op1.getOperand(0).getOpcode() == ISD::SHL || 
+    if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
         Op1.getOperand(0).getOpcode() == ISD::SRL) {
-      if (ConstantSDNode *CN = 
+      if (ConstantSDNode *CN =
           dyn_cast<ConstantSDNode>(Op1.getOperand(0).getOperand(1).Val)) {
-        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? 
+        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
           CN->getValue() : 32 - CN->getValue();
         Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
       }
     } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
                Op0.getOperand(0).getOpcode() == ISD::SRL) {
-      if (ConstantSDNode *CN = 
+      if (ConstantSDNode *CN =
           dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(1).Val)) {
         std::swap(Op0, Op1);
         std::swap(TgtMask, InsMask);
-        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ? 
+        Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
           CN->getValue() : 32 - CN->getValue();
         Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
       }
@@ -1878,7 +1878,7 @@
         return SelectExpr(BuildSDIVSequence(N));
       else
         return SelectExpr(BuildUDIVSequence(N));
-    }    
+    }
     Tmp1 = SelectExpr(N.getOperand(0));
     Tmp2 = SelectExpr(N.getOperand(1));
     switch (DestType) {


Index: llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.11 llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.12
--- llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp:1.11	Sat Jun 18 12:37:34 2005
+++ llvm/lib/Target/PowerPC/PowerPCBranchSelector.cpp	Wed Jul 27 01:12:33 2005
@@ -92,7 +92,7 @@
           if (OpcodeToReplace == PPC::COND_BRANCH) {
             MachineBasicBlock::iterator MBBJ = MBBI;
             ++MBBJ;
-            
+
             // condbranch operands:
             // 0. CR0 register
             // 1. bc opcode


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.56 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.57
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.56	Thu Jul 21 15:44:43 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Wed Jul 27 01:12:33 2005
@@ -136,7 +136,7 @@
   PICEnabled = false;
 
   bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
-  
+
   if (EnablePPCLSR) {
     PM.add(createLoopStrengthReducePass());
     PM.add(createCFGSimplificationPass());