[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp PPC32ISelPattern.cpp PowerPCAsmPrinter.cpp PowerPCInstrInfo.td PowerPCTargetMachine.cpp

Nate Begeman natebegeman at mac.com
Wed Jul 20 15:42:11 PDT 2005



Changes in directory llvm/lib/Target/PowerPC:

PPC32CodeEmitter.cpp updated: 1.30 -> 1.31
PPC32ISelPattern.cpp updated: 1.100 -> 1.101
PowerPCAsmPrinter.cpp updated: 1.79 -> 1.80
PowerPCInstrInfo.td updated: 1.73 -> 1.74
PowerPCTargetMachine.cpp updated: 1.53 -> 1.54
---
Log message:

Generate mfocrf when targeting g5.  Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.


---
Diffs of the changes:  (+54 -22)

 PPC32CodeEmitter.cpp     |    4 ++--
 PPC32ISelPattern.cpp     |   21 ++++++++++++++++++---
 PowerPCAsmPrinter.cpp    |   37 +++++++++++++++++++++++--------------
 PowerPCInstrInfo.td      |   10 +++++++++-
 PowerPCTargetMachine.cpp |    4 ++--
 5 files changed, 54 insertions(+), 22 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp
diff -u llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.30 llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.31
--- llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp:1.30	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32CodeEmitter.cpp	Wed Jul 20 17:42:00 2005
@@ -187,9 +187,9 @@
   if (MO.isRegister()) {
     rv = enumRegToMachineReg(MO.getReg());
 
-    // Special encoding for MTCRF and MFCRF, which uses a bit mask for the
+    // Special encoding for MTCRF and MFOCRF, which uses a bit mask for the
     // register, not the register number directly.
-    if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFCRF) &&
+    if ((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MFOCRF) &&
         (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7)) {
       rv = 0x80 >> rv;
     }


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.100 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.101
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.100	Tue Jul 19 11:51:05 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Jul 20 17:42:00 2005
@@ -35,6 +35,11 @@
 #include <algorithm>
 using namespace llvm;
 
+// FIXME: temporary.
+#include "llvm/Support/CommandLine.h"
+static cl::opt<bool> EnableGPOPT("enable-gpopt", cl::Hidden,
+                                 cl::desc("Enable optimizations for GP cpus"));
+
 //===----------------------------------------------------------------------===//
 //  PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
 namespace {
@@ -67,13 +72,17 @@
       // We don't support sin/cos/sqrt/fmod
       setOperationAction(ISD::FSIN , MVT::f64, Expand);
       setOperationAction(ISD::FCOS , MVT::f64, Expand);
-      setOperationAction(ISD::FSQRT, MVT::f64, Expand);
       setOperationAction(ISD::SREM , MVT::f64, Expand);
       setOperationAction(ISD::FSIN , MVT::f32, Expand);
       setOperationAction(ISD::FCOS , MVT::f32, Expand);
-      setOperationAction(ISD::FSQRT, MVT::f32, Expand);
       setOperationAction(ISD::SREM , MVT::f32, Expand);
 
+      // If we're enabling GP optimizations, use hardware square root
+      if (!EnableGPOPT) {
+        setOperationAction(ISD::FSQRT, MVT::f64, Expand);
+        setOperationAction(ISD::FSQRT, MVT::f32, Expand);
+      }
+            
       //PowerPC does not have CTPOP or CTTZ
       setOperationAction(ISD::CTPOP, MVT::i32  , Expand);
       setOperationAction(ISD::CTTZ , MVT::i32  , Expand);
@@ -961,7 +970,7 @@
 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
   unsigned IntCR = MakeReg(MVT::i32);
   BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
-  BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
+  BuildMI(BB, EnableGPOPT ? PPC::MFOCRF : PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
   if (Inv) {
     unsigned Tmp1 = MakeReg(MVT::i32);
     BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
@@ -2273,6 +2282,12 @@
     BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
     return Result;
 
+  case ISD::FSQRT:
+    Tmp1 = SelectExpr(N.getOperand(0));
+    Opc = DestType == MVT::f64 ? PPC::FSQRT : PPC::FSQRTS;
+    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
+    return Result;
+
   case ISD::FP_ROUND:
     assert (DestType == MVT::f32 &&
             N.getOperand(0).getValueType() == MVT::f64 &&


Index: llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.79 llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.80
--- llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp:1.79	Tue Jul 12 13:34:15 2005
+++ llvm/lib/Target/PowerPC/PowerPCAsmPrinter.cpp	Wed Jul 20 17:42:00 2005
@@ -60,6 +60,21 @@
       return static_cast<PowerPCTargetMachine&>(TM);
     }
 
+    unsigned enumRegToMachineReg(unsigned enumReg) {
+      switch (enumReg) {
+      default: assert(0 && "Unhandled register!"); break;
+      case PPC::CR0:  return  0;
+      case PPC::CR1:  return  1;
+      case PPC::CR2:  return  2;
+      case PPC::CR3:  return  3;
+      case PPC::CR4:  return  4;
+      case PPC::CR5:  return  5;
+      case PPC::CR6:  return  6;
+      case PPC::CR7:  return  7;
+      }
+      abort();
+    }
+
     /// printInstruction - This method is automatically generated by tablegen
     /// from the instruction set description.  This method returns true if the
     /// machine instruction was sufficiently described to print it, otherwise it
@@ -141,22 +156,16 @@
                        MVT::ValueType VT) {
       unsigned char value = MI->getOperand(OpNo).getImmedValue();
       assert(value <= 3 && "Invalid crbit argument!");
-      unsigned RegNo, CCReg = MI->getOperand(OpNo-1).getReg();
-      switch (CCReg) {
-      case PPC::CR0:  RegNo = 0; break;
-      case PPC::CR1:  RegNo = 1; break;
-      case PPC::CR2:  RegNo = 2; break;
-      case PPC::CR3:  RegNo = 3; break;
-      case PPC::CR4:  RegNo = 4; break;
-      case PPC::CR5:  RegNo = 5; break;
-      case PPC::CR6:  RegNo = 6; break;
-      case PPC::CR7:  RegNo = 7; break;
-      default:
-        std::cerr << "Unhandled reg in enumRegToRealReg!\n";
-        abort();
-      }
+      unsigned CCReg = MI->getOperand(OpNo-1).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
       O << 4 * RegNo + value;
     }
+    void printcrbitm(const MachineInstr *MI, unsigned OpNo,
+                       MVT::ValueType VT) {
+      unsigned CCReg = MI->getOperand(OpNo).getReg();
+      unsigned RegNo = enumRegToMachineReg(CCReg);
+      O << (0x80 >> RegNo);
+    }
 
     virtual void printConstantPool(MachineConstantPool *MCP) = 0;
     virtual bool runOnMachineFunction(MachineFunction &F) = 0;


Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.73 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.74
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.73	Sun May 15 15:11:44 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td	Wed Jul 20 17:42:00 2005
@@ -55,6 +55,9 @@
 def crbit: Operand<i8> {
   let PrintMethod = "printcrbit";
 }
+def crbitm: Operand<i8> {
+  let PrintMethod = "printcrbitm";
+}
 
 // Pseudo-instructions:
 def PHI : Pseudo<(ops), "; PHI">;
@@ -314,6 +317,11 @@
                       "fneg $frD, $frB">;
 def FRSP   : XForm_26<63, 12, (ops FPRC:$frD, FPRC:$frB),
                       "frsp $frD, $frB">;
+def FSQRT  : XForm_26<63, 22, (ops FPRC:$frD, FPRC:$frB),
+                      "fsqrt $frD, $frB">;
+def FSQRTS : XForm_26<59, 22, (ops FPRC:$frD, FPRC:$frB),
+                      "fsqrts $frD, $frB">;
+                      
 let isStore = 1 in {
 def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
                      "stfsx $frS, $rA, $rB">;
@@ -360,7 +368,7 @@
 def MFCR  : XFXForm_3<31, 19, (ops GPRC:$rT), "mfcr $rT">;
 def MTCRF : XFXForm_5<31, 0, 144, (ops CRRC:$FXM, GPRC:$rS),
                       "mtcrf $FXM, $rS">;
-def MFCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, CRRC:$FXM),
+def MFOCRF : XFXForm_5<31, 1, 19, (ops GPRC:$rT, crbitm:$FXM),
                       "mfcr $rT, $FXM">;
 def MTCTR : XFXForm_7_ext<31, 467, 288, (ops GPRC:$rS), "mtctr $rS">;
 def MTLR  : XFXForm_7_ext<31, 467, 256, (ops GPRC:$rS), "mtlr $rS">;


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.53 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.54
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.53	Tue Jul 19 11:51:05 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Wed Jul 20 17:42:00 2005
@@ -170,14 +170,14 @@
 ///
 PPC32TargetMachine::PPC32TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC32ID, IL,
-                         TargetData(PPC32ID,false,4,4,4,4,4,4,2,1,1),
+                         TargetData(PPC32ID,false,4,4,8,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, false)), JITInfo(*this) {}
 
 /// PPC64TargetMachine ctor - Create a LP64 architecture model
 ///
 PPC64TargetMachine::PPC64TargetMachine(const Module &M, IntrinsicLowering *IL)
   : PowerPCTargetMachine(PPC64ID, IL,
-                         TargetData(PPC64ID,false,8,4,4,4,4,4,2,1,1),
+                         TargetData(PPC64ID,false,8,4,8,4,4,4,2,1,1),
                          PowerPCFrameInfo(*this, true)) {}
 
 unsigned PPC32TargetMachine::getModuleMatchQuality(const Module &M) {






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