[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC64ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.98 -> 1.99
PPC64ISelPattern.cpp updated: 1.24 -> 1.25
---
Log message:

Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
This is the last MVTSDNode.

This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.

Also, remove some uses of dyn_cast that should really be cast (which is
cheaper in a release build).


---
Diffs of the changes:  (+4 -4)

 PPC32ISelPattern.cpp |    4 ++--
 PPC64ISelPattern.cpp |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.98 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.99
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.98	Sat Jul  9 19:29:18 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Sat Jul  9 20:56:13 2005
@@ -1690,7 +1690,7 @@
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD: {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
-      Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
+      Node->getValueType(0) : cast<VTSDNode>(Node->getOperand(3))->getVT();
     bool sext = (ISD::SEXTLOAD == opcode);
 
     // Make sure we generate both values.
@@ -1828,7 +1828,7 @@
   case ISD::SIGN_EXTEND:
   case ISD::SIGN_EXTEND_INREG:
     Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+    switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i16:
       BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.24 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.25
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.24	Sat Jul  9 19:29:18 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Sat Jul  9 20:56:13 2005
@@ -1030,7 +1030,7 @@
   case ISD::ZEXTLOAD:
   case ISD::SEXTLOAD: {
     MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
-      Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
+      Node->getValueType(0) : cast<VTSDNode>(Node->getOperand(3))->getVT();
     bool sext = (ISD::SEXTLOAD == opcode);
 
     // Make sure we generate both values.
@@ -1166,7 +1166,7 @@
   case ISD::SIGN_EXTEND:
   case ISD::SIGN_EXTEND_INREG:
     Tmp1 = SelectExpr(N.getOperand(0));
-    switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
+    switch(cast<VTSDNode>(Node->getOperand(1))->getVT()) {
     default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
     case MVT::i32:
       BuildMI(BB, PPC::EXTSW, 1, Result).addReg(Tmp1);