[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp SelectionDAGPrinter.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sat Jul 9 18:55:44 PDT 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
LegalizeDAG.cpp updated: 1.137 -> 1.138
SelectionDAG.cpp updated: 1.124 -> 1.125
SelectionDAGPrinter.cpp updated: 1.11 -> 1.12
---
Log message:
Change *EXTLOAD to use an VTSDNode operand instead of being an MVTSDNode.
This is the last MVTSDNode.
This allows us to eliminate a bunch of special case code for handling
MVTSDNodes.
---
Diffs of the changes: (+60 -90)
LegalizeDAG.cpp | 42 +++++++++----------
SelectionDAG.cpp | 106 +++++++++++++++++-------------------------------
SelectionDAGPrinter.cpp | 2
3 files changed, 60 insertions(+), 90 deletions(-)
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.137 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.138
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.137 Sat Jul 9 19:29:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sat Jul 9 20:55:33 2005
@@ -317,8 +317,8 @@
SDOperand CPIdx = DAG.getConstantPool(CP->getConstantPoolIndex(LLVMC),
TLI.getPointerTy());
if (Extend) {
- Result = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(), CPIdx,
- DAG.getSrcValue(NULL), MVT::f32);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+ CPIdx, DAG.getSrcValue(NULL), MVT::f32);
} else {
Result = DAG.getLoad(VT, DAG.getEntryNode(), CPIdx,
DAG.getSrcValue(NULL));
@@ -495,13 +495,13 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
- MVT::ValueType SrcVT = cast<MVTSDNode>(Node)->getExtraValueType();
+ MVT::ValueType SrcVT = cast<VTSDNode>(Node->getOperand(3))->getVT();
switch (TLI.getOperationAction(Node->getOpcode(), SrcVT)) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Promote:
assert(SrcVT == MVT::i1 && "Can only promote EXTLOAD from i1 -> i8!");
- Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
- Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
+ Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
+ Tmp1, Tmp2, Node->getOperand(2), MVT::i8);
// Since loads produce two values, make sure to remember that we legalized
// both of them.
AddLegalizedOperand(SDOperand(Node, 0), Result);
@@ -511,8 +511,8 @@
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0) ||
Tmp2 != Node->getOperand(1))
- Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0),
- Tmp1, Tmp2, Node->getOperand(2), SrcVT);
+ Result = DAG.getExtLoad(Node->getOpcode(), Node->getValueType(0),
+ Tmp1, Tmp2, Node->getOperand(2), SrcVT);
else
Result = SDOperand(Node, 0);
@@ -534,8 +534,8 @@
"EXTLOAD should always be supported!");
// Turn the unsupported load into an EXTLOAD followed by an explicit
// zero/sign extend inreg.
- Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
- Tmp1, Tmp2, Node->getOperand(2), SrcVT);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
+ Tmp1, Tmp2, Node->getOperand(2), SrcVT);
SDOperand ValRes;
if (Node->getOpcode() == ISD::SEXTLOAD)
ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, Result.getValueType(),
@@ -1362,8 +1362,9 @@
else {
assert(Node->getValueType(0) == MVT::f64 && "Unexpected conversion");
FudgeInReg =
- LegalizeOp(DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
- CPIdx, DAG.getSrcValue(NULL), MVT::f32));
+ LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, MVT::f64,
+ DAG.getEntryNode(), CPIdx,
+ DAG.getSrcValue(NULL), MVT::f32));
}
Result = DAG.getNode(ISD::ADD, Node->getValueType(0), Tmp1, FudgeInReg);
break;
@@ -1451,7 +1452,7 @@
case TargetLowering::Legal:
if (Tmp1 != Node->getOperand(0))
Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,
- ExtraVT);
+ DAG.getValueType(ExtraVT));
break;
case TargetLowering::Expand:
// If this is an integer extend and shifts are supported, do that.
@@ -1482,8 +1483,9 @@
Result = DAG.getNode(ISD::TRUNCSTORE, MVT::Other, DAG.getEntryNode(),
Node->getOperand(0), StackSlot,
DAG.getSrcValue(NULL), DAG.getValueType(ExtraVT));
- Result = DAG.getNode(ISD::EXTLOAD, Node->getValueType(0),
- Result, StackSlot, DAG.getSrcValue(NULL), ExtraVT);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, Node->getValueType(0),
+ Result, StackSlot, DAG.getSrcValue(NULL),
+ ExtraVT);
} else {
assert(0 && "Unknown op");
}
@@ -1768,11 +1770,11 @@
Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the pointer.
// FIXME: When the DAG combiner exists, change this to use EXTLOAD!
if (MVT::isInteger(NVT))
- Result = DAG.getNode(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2),
- VT);
+ Result = DAG.getExtLoad(ISD::ZEXTLOAD, NVT, Tmp1, Tmp2,
+ Node->getOperand(2), VT);
else
- Result = DAG.getNode(ISD::EXTLOAD, NVT, Tmp1, Tmp2, Node->getOperand(2),
- VT);
+ Result = DAG.getExtLoad(ISD::EXTLOAD, NVT, Tmp1, Tmp2,
+ Node->getOperand(2), VT);
// Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), Result.getValue(1));
@@ -2277,8 +2279,8 @@
DAG.getSrcValue(NULL));
else {
assert(DestTy == MVT::f64 && "Unexpected conversion");
- FudgeInReg = DAG.getNode(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
- CPIdx, DAG.getSrcValue(NULL), MVT::f32);
+ FudgeInReg = DAG.getExtLoad(ISD::EXTLOAD, MVT::f64, DAG.getEntryNode(),
+ CPIdx, DAG.getSrcValue(NULL), MVT::f32);
}
return DAG.getNode(ISD::ADD, DestTy, SignedConv, FudgeInReg);
}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.124 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.125
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.124 Sat Jul 9 19:29:03 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sat Jul 9 20:55:33 2005
@@ -235,18 +235,6 @@
cast<SetCCSDNode>(N)->getCondition(),
N->getValueType(0))));
break;
- case ISD::EXTLOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD: {
- EVTStruct NN;
- NN.Opcode = N->getOpcode();
- NN.VT = N->getValueType(0);
- NN.EVT = cast<MVTSDNode>(N)->getExtraValueType();
- for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- NN.Ops.push_back(N->getOperand(i));
- MVTSDNodes.erase(NN);
- break;
- }
default:
if (N->getNumOperands() == 1)
UnaryOps.erase(std::make_pair(N->getOpcode(),
@@ -795,7 +783,7 @@
TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
case ISD::ZEXTLOAD:
- SrcBits = MVT::getSizeInBits(cast<MVTSDNode>(Op)->getExtraValueType());
+ SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::ZERO_EXTEND:
SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
@@ -1248,7 +1236,7 @@
// If we are sign extending a sextload, return just the load.
if (N1.getOpcode() == ISD::SEXTLOAD)
- if (cast<MVTSDNode>(N1)->getExtraValueType() <= EVT)
+ if (cast<VTSDNode>(N1.getOperand(3))->getVT() <= EVT)
return N1;
// If we are extending the result of a setcc, and we already know the
@@ -1335,6 +1323,22 @@
return SDOperand(N, 0);
}
+
+SDOperand SelectionDAG::getExtLoad(unsigned Opcode, MVT::ValueType VT,
+ SDOperand Chain, SDOperand Ptr, SDOperand SV,
+ MVT::ValueType EVT) {
+ std::vector<SDOperand> Ops;
+ Ops.reserve(4);
+ Ops.push_back(Chain);
+ Ops.push_back(Ptr);
+ Ops.push_back(SV);
+ Ops.push_back(getValueType(EVT));
+ std::vector<MVT::ValueType> VTs;
+ VTs.reserve(2);
+ VTs.push_back(VT); VTs.push_back(MVT::Other); // Add token chain.
+ return getNode(Opcode, VTs, Ops);
+}
+
SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
SDOperand N1, SDOperand N2, SDOperand N3) {
// Perform various simplifications.
@@ -1547,11 +1551,29 @@
if (ResultTys.size() == 1)
return getNode(Opcode, ResultTys[0], Ops);
+ switch (Opcode) {
+ case ISD::EXTLOAD:
+ case ISD::SEXTLOAD:
+ case ISD::ZEXTLOAD: {
+ MVT::ValueType EVT = cast<VTSDNode>(Ops[3])->getVT();
+ assert(Ops.size() == 4 && ResultTys.size() == 2 && "Bad *EXTLOAD!");
+ // If they are asking for an extending load from/to the same thing, return a
+ // normal load.
+ if (ResultTys[0] == EVT)
+ return getLoad(ResultTys[0], Ops[0], Ops[1], Ops[2]);
+ assert(EVT < ResultTys[0] &&
+ "Should only be an extending load, not truncating!");
+ assert((Opcode == ISD::EXTLOAD || MVT::isInteger(ResultTys[0])) &&
+ "Cannot sign/zero extend a FP load!");
+ assert(MVT::isInteger(ResultTys[0]) == MVT::isInteger(EVT) &&
+ "Cannot convert from FP to Int or Int -> FP!");
+ break;
+ }
+
// FIXME: figure out how to safely handle things like
// int foo(int x) { return 1 << (x & 255); }
// int bar() { return foo(256); }
#if 0
- switch (Opcode) {
case ISD::SRA_PARTS:
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
@@ -1567,8 +1589,8 @@
return getNode(Opcode, VT, N1, N2, N3.getOperand(0));
}
break;
- }
#endif
+ }
// Memoize the node.
SDNode *&N = ArbitraryNodes[std::make_pair(Opcode, std::make_pair(ResultTys,
@@ -1580,56 +1602,6 @@
return SDOperand(N, 0);
}
-
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
- MVT::ValueType EVT) {
- EVTStruct NN;
- NN.Opcode = Opcode;
- NN.VT = VT;
- NN.EVT = EVT;
- NN.Ops.push_back(N1);
-
- SDNode *&N = MVTSDNodes[NN];
- if (N) return SDOperand(N, 0);
- N = new MVTSDNode(Opcode, VT, N1, EVT);
- AllNodes.push_back(N);
- return SDOperand(N, 0);
-}
-
-SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,SDOperand N1,
- SDOperand N2, SDOperand N3, MVT::ValueType EVT) {
- switch (Opcode) {
- default: assert(0 && "Bad opcode for this accessor!");
- case ISD::EXTLOAD:
- case ISD::SEXTLOAD:
- case ISD::ZEXTLOAD:
- // If they are asking for an extending load from/to the same thing, return a
- // normal load.
- if (VT == EVT)
- return getLoad(VT, N1, N2, N3);
- assert(EVT < VT && "Should only be an extending load, not truncating!");
- assert((Opcode == ISD::EXTLOAD || MVT::isInteger(VT)) &&
- "Cannot sign/zero extend a FP load!");
- assert(MVT::isInteger(VT) == MVT::isInteger(EVT) &&
- "Cannot convert from FP to Int or Int -> FP!");
- break;
- }
-
- EVTStruct NN;
- NN.Opcode = Opcode;
- NN.VT = VT;
- NN.EVT = EVT;
- NN.Ops.push_back(N1);
- NN.Ops.push_back(N2);
- NN.Ops.push_back(N3);
-
- SDNode *&N = MVTSDNodes[NN];
- if (N) return SDOperand(N, 0);
- N = new MVTSDNode(Opcode, VT, MVT::Other, N1, N2, N3, EVT);
- AllNodes.push_back(N);
- return SDOperand(N, 0);
-}
-
/// hasNUsesOfValue - Return true if there are exactly NUSES uses of the
/// indicated value. This method ignores uses of other values defined by this
/// operation.
@@ -1836,8 +1808,6 @@
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(this)) {
std::cerr << "'" << ES->getSymbol() << "'";
- } else if (const MVTSDNode *M = dyn_cast<MVTSDNode>(this)) {
- std::cerr << " - Ty = " << MVT::getValueTypeString(M->getExtraValueType());
} else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(this)) {
if (M->getValue())
std::cerr << "<" << M->getValue() << ":" << M->getOffset() << ">";
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.11 llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.12
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp:1.11 Sun May 8 23:08:27 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp Sat Jul 9 20:55:33 2005
@@ -88,8 +88,6 @@
} else if (const ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Node)) {
Op += "'" + std::string(ES->getSymbol()) + "'";
- } else if (const MVTSDNode *M = dyn_cast<MVTSDNode>(Node)) {
- Op = Op + " ty=" + MVT::getValueTypeString(M->getExtraValueType());
} else if (const SrcValueSDNode *M = dyn_cast<SrcValueSDNode>(Node)) {
if (M->getValue())
Op += "<" + M->getValue()->getName() + ":" + itostr(M->getOffset()) + ">";
More information about the llvm-commits
mailing list