[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp AlphaInstrInfo.td
Andrew Lenharth
alenhar2 at cs.uiuc.edu
Wed Jun 22 10:19:57 PDT 2005
Changes in directory llvm/lib/Target/Alpha:
AlphaISelPattern.cpp updated: 1.123 -> 1.124
AlphaInstrInfo.td updated: 1.43 -> 1.44
---
Log message:
Make it easier to find alpha stuff in doxygen, and fixup labeling
of memory instructions in the assembly, to allow later linking
of traces with LLVM Value*s.
---
Diffs of the changes: (+52 -17)
AlphaISelPattern.cpp | 67 ++++++++++++++++++++++++++++++++++++++-------------
AlphaInstrInfo.td | 2 -
2 files changed, 52 insertions(+), 17 deletions(-)
Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.123 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.124
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.123 Sat Jun 18 13:34:52 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp Wed Jun 22 12:19:45 2005
@@ -15,6 +15,7 @@
#include "AlphaRegisterInfo.h"
#include "llvm/Constants.h" // FIXME: REMOVE
#include "llvm/Function.h"
+#include "llvm/Module.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
#include "llvm/CodeGen/MachineFunction.h"
@@ -443,7 +444,7 @@
/// ISel - Alpha specific code to select Alpha machine instructions for
/// SelectionDAG operations.
//===--------------------------------------------------------------------===//
-class ISel : public SelectionDAGISel {
+class AlphaISel : public SelectionDAGISel {
/// AlphaLowering - This object fully describes how to lower LLVM code to an
/// Alpha-specific SelectionDAG.
@@ -468,7 +469,7 @@
int max_depth;
public:
- ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
+ AlphaISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
{}
/// InstructionSelectBasicBlock - This callback is invoked by
@@ -519,7 +520,7 @@
};
}
-void ISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
+void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
// If this function has live-in values, emit the copies from pregs to vregs at
// the top of the function, before anything else.
MachineBasicBlock *BB = MF.begin();
@@ -542,8 +543,9 @@
//Find the offset of the arg in it's parent's function
static int getValueOffset(const Value* v)
{
+ static int uniqneg = -1;
if (v == NULL)
- return 0;
+ return uniqneg--;
const Instruction* itarget = dyn_cast<Instruction>(v);
const BasicBlock* btarget = itarget->getParent();
@@ -559,6 +561,24 @@
return i;
}
+//Find the offset of the function in it's module
+static int getFunctionOffset(const Function* fun)
+{
+ const Module* M = fun->getParent();
+
+ //offset due to earlier BBs
+ int i = 0;
+ for(Module::const_iterator ii = M->begin(); &*ii != fun; ++ii)
+ ++i;
+
+ return i;
+}
+
+static int getUID()
+{
+ static int id = 0;
+ return ++id;
+}
//Factorize a number using the list of constants
static bool factorize(int v[], int res[], int size, uint64_t c)
@@ -680,7 +700,7 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand ISel::BuildSDIVSequence(SDOperand N) {
+SDOperand AlphaISel::BuildSDIVSequence(SDOperand N) {
int64_t d = (int64_t)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
ms magics = magic(d);
// Multiply the numerator (operand 0) by the magic value
@@ -706,7 +726,7 @@
/// return a DAG expression to select that will generate the same value by
/// multiplying by a magic number. See:
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
-SDOperand ISel::BuildUDIVSequence(SDOperand N) {
+SDOperand AlphaISel::BuildUDIVSequence(SDOperand N) {
unsigned d =
(unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
mu magics = magicu(d);
@@ -781,7 +801,7 @@
}
}
-void ISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
+void AlphaISel::MoveFP2Int(unsigned src, unsigned dst, bool isDouble)
{
unsigned Opc;
if (EnableAlphaFTOI) {
@@ -801,7 +821,7 @@
}
}
-void ISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
+void AlphaISel::MoveInt2FP(unsigned src, unsigned dst, bool isDouble)
{
unsigned Opc;
if (EnableAlphaFTOI) {
@@ -821,7 +841,7 @@
}
}
-bool ISel::SelectFPSetCC(SDOperand N, unsigned dst)
+bool AlphaISel::SelectFPSetCC(SDOperand N, unsigned dst)
{
SDNode *Node = N.Val;
unsigned Opc, Tmp1, Tmp2, Tmp3;
@@ -880,7 +900,7 @@
}
//Check to see if the load is a constant offset from a base register
-void ISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
+void AlphaISel::SelectAddr(SDOperand N, unsigned& Reg, long& offset)
{
unsigned opcode = N.getOpcode();
if (opcode == ISD::ADD) {
@@ -904,7 +924,7 @@
return;
}
-void ISel::SelectBranchCC(SDOperand N)
+void AlphaISel::SelectBranchCC(SDOperand N)
{
assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
MachineBasicBlock *Dest =
@@ -1015,7 +1035,7 @@
abort(); //Should never be reached
}
-unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
+unsigned AlphaISel::SelectExprFP(SDOperand N, unsigned Result)
{
unsigned Tmp1, Tmp2, Tmp3;
unsigned Opc = 0;
@@ -1168,7 +1188,8 @@
if (EnableAlphaLSMark)
{
int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
- BuildMI(BB, Alpha::MEMLABEL, 2).addImm(i);
+ int j = getFunctionOffset(BB->getParent()->getFunction());
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
}
if (Address.getOpcode() == ISD::GlobalAddress) {
@@ -1318,7 +1339,7 @@
return 0;
}
-unsigned ISel::SelectExpr(SDOperand N) {
+unsigned AlphaISel::SelectExpr(SDOperand N) {
unsigned Result;
unsigned Tmp1, Tmp2 = 0, Tmp3;
unsigned Opc = 0;
@@ -1482,6 +1503,13 @@
assert(opcode != ISD::SEXTLOAD && "Not zext"); break;
}
+ if (EnableAlphaLSMark)
+ {
+ int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(2))->getValue());
+ int j = getFunctionOffset(BB->getParent()->getFunction());
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ }
+
if (Address.getOpcode() == ISD::GlobalAddress) {
AlphaLowering.restoreGP(BB);
Opc = GetSymVersion(Opc);
@@ -2231,7 +2259,7 @@
return 0;
}
-void ISel::Select(SDOperand N) {
+void AlphaISel::Select(SDOperand N) {
unsigned Tmp1, Tmp2, Opc;
unsigned opcode = N.getOpcode();
@@ -2353,6 +2381,13 @@
}
}
+ if (EnableAlphaLSMark)
+ {
+ int i = getValueOffset(dyn_cast<SrcValueSDNode>(N.getOperand(3))->getValue());
+ int j = getFunctionOffset(BB->getParent()->getFunction());
+ BuildMI(BB, Alpha::MEMLABEL, 3).addImm(j).addImm(i).addImm(getUID());
+ }
+
if (Address.getOpcode() == ISD::GlobalAddress)
{
AlphaLowering.restoreGP(BB);
@@ -2411,6 +2446,6 @@
/// description file.
///
FunctionPass *llvm::createAlphaPatternInstructionSelector(TargetMachine &TM) {
- return new ISel(TM);
+ return new AlphaISel(TM);
}
Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.43 llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.44
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.43 Mon Jun 6 14:03:55 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td Wed Jun 22 12:19:45 2005
@@ -31,7 +31,7 @@
def ADJUSTSTACKDOWN : PseudoInstAlpha<(ops ), "ADJDOWN">;
def ALTENT : PseudoInstAlpha<(ops s64imm:$TARGET), "$TARGET:\n">;
def PCLABEL : PseudoInstAlpha<(ops s64imm:$num), "PCMARKER_$num:\n">;
-def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i), "LSMARKER_$i:\n">;
+def MEMLABEL : PseudoInstAlpha<(ops s64imm:$i, s64imm:$j, s64imm:$k), "LSMARKER$$$i$$$j$$$k:\n">;
//*****************
//These are shortcuts, the assembler expands them
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