[llvm-commits] CVS: llvm/lib/Target/X86/X86ISelPattern.cpp X86ISelSimple.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/X86:

X86ISelPattern.cpp updated: 1.128 -> 1.129
X86ISelSimple.cpp updated: 1.318 -> 1.319
---
Log message:

Fix UnitTests/2005-05-13-SDivTwo.c


---
Diffs of the changes:  (+4 -3)

 X86ISelPattern.cpp |    5 +++--
 X86ISelSimple.cpp  |    2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)


Index: llvm/lib/Target/X86/X86ISelPattern.cpp
diff -u llvm/lib/Target/X86/X86ISelPattern.cpp:1.128 llvm/lib/Target/X86/X86ISelPattern.cpp:1.129
--- llvm/lib/Target/X86/X86ISelPattern.cpp:1.128	Fri May 13 16:44:04 2005
+++ llvm/lib/Target/X86/X86ISelPattern.cpp	Fri May 13 16:48:20 2005
@@ -2675,7 +2675,6 @@
         }
         if (RHS && (RHS & (RHS-1)) == 0) {   // Signed division by power of 2?
           unsigned Log = log2(RHS);
-          unsigned TmpReg = MakeReg(N.getValueType());
           unsigned SAROpc, SHROpc, ADDOpc, NEGOpc;
           switch (N.getValueType()) {
           default: assert("Unknown type to signed divide!");
@@ -2698,10 +2697,12 @@
             NEGOpc = X86::NEG32r;
             break;
           }
+          unsigned RegSize = MVT::getSizeInBits(N.getValueType());
           Tmp1 = SelectExpr(N.getOperand(0));
+          unsigned TmpReg = MakeReg(N.getValueType());
           BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
           unsigned TmpReg2 = MakeReg(N.getValueType());
-          BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
+          BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(RegSize-Log);
           unsigned TmpReg3 = MakeReg(N.getValueType());
           BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
 


Index: llvm/lib/Target/X86/X86ISelSimple.cpp
diff -u llvm/lib/Target/X86/X86ISelSimple.cpp:1.318 llvm/lib/Target/X86/X86ISelSimple.cpp:1.319
--- llvm/lib/Target/X86/X86ISelSimple.cpp:1.318	Fri May 13 16:44:04 2005
+++ llvm/lib/Target/X86/X86ISelSimple.cpp	Fri May 13 16:48:20 2005
@@ -2924,7 +2924,7 @@
           .addReg(Op0Reg).addImm(Log-1);
         unsigned TmpReg2 = makeAnotherReg(Op0->getType());
         BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
-          .addReg(TmpReg).addImm(32-Log);
+          .addReg(TmpReg).addImm(CI->getType()->getPrimitiveSizeInBits()-Log);
         unsigned TmpReg3 = makeAnotherReg(Op0->getType());
         BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
           .addReg(Op0Reg).addReg(TmpReg2);