[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Chris Lattner
lattner at cs.uiuc.edu
Wed May 11 23:27:21 PDT 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.107 -> 1.108
---
Log message:
handle a common case generated by the uint64 -> FP code path better
---
Diffs of the changes: (+17 -1)
SelectionDAG.cpp | 18 +++++++++++++++++-
1 files changed, 17 insertions(+), 1 deletion(-)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.107 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.108
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.107 Wed May 11 19:17:04 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Thu May 12 01:27:02 2005
@@ -1299,7 +1299,7 @@
N2.getOperand(0) == N3)
return getNode(ISD::FABS, VT, N3);
}
- // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1, A)
+ // select (setlt X, 0), A, 0 -> and (sra X, size(X)-1), A
if (ConstantSDNode *CN =
dyn_cast<ConstantSDNode>(SetCC->getOperand(1)))
if (CN->getValue() == 0 && N3C && N3C->getValue() == 0)
@@ -1307,6 +1307,22 @@
MVT::ValueType XType = SetCC->getOperand(0).getValueType();
MVT::ValueType AType = N2.getValueType();
if (XType >= AType) {
+ // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
+ // single-bit constant. FIXME: remove once the dag combiner
+ // exists.
+ if (ConstantSDNode *AC = dyn_cast<ConstantSDNode>(N2))
+ if ((AC->getValue() & (AC->getValue()-1)) == 0) {
+ unsigned ShCtV = ExactLog2(AC->getValue());
+ ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
+ SDOperand ShCt = getConstant(ShCtV, TLI.getShiftAmountTy());
+ SDOperand Shift = getNode(ISD::SRL, XType,
+ SetCC->getOperand(0), ShCt);
+ if (XType > AType)
+ Shift = getNode(ISD::TRUNCATE, AType, Shift);
+ return getNode(ISD::AND, AType, Shift, N2);
+ }
+
+
SDOperand Shift = getNode(ISD::SRA, XType, SetCC->getOperand(0),
getConstant(MVT::getSizeInBits(XType)-1,
TLI.getShiftAmountTy()));
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