[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.91 -> 1.92
---
Log message:

Legalize FSQRT, FSIN, FCOS nodes, patch contributed by Morten Ofstad



---
Diffs of the changes:  (+13 -0)

 LegalizeDAG.cpp |   13 +++++++++++++
 1 files changed, 13 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.91 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.92
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.91	Wed Apr 27 15:10:01 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Thu Apr 28 16:44:33 2005
@@ -990,6 +990,9 @@
     // Unary operators
   case ISD::FABS:
   case ISD::FNEG:
+  case ISD::FSQRT:
+  case ISD::FSIN:
+  case ISD::FCOS:
     Tmp1 = LegalizeOp(Node->getOperand(0));
     switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
     case TargetLowering::Legal:
@@ -1335,6 +1338,16 @@
     // precision, and these operations don't modify precision at all.
     break;
 
+  case ISD::FSQRT:
+  case ISD::FSIN:
+  case ISD::FCOS:
+    Tmp1 = PromoteOp(Node->getOperand(0));
+    assert(Tmp1.getValueType() == NVT);
+    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1);
+    if(NoExcessFPPrecision)
+      Result = DAG.getNode(ISD::FP_ROUND_INREG, NVT, Result, VT);
+    break;
+
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR: