[llvm-commits] CVS: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp SparcV8ISelSimple.cpp SparcV8TargetMachine.cpp
Misha Brukman
brukman at cs.uiuc.edu
Fri Apr 22 11:06:12 PDT 2005
Changes in directory llvm/lib/Target/SparcV8:
SparcV8AsmPrinter.cpp updated: 1.32 -> 1.33
SparcV8ISelSimple.cpp updated: 1.90 -> 1.91
SparcV8TargetMachine.cpp updated: 1.26 -> 1.27
---
Log message:
Convert tabs to spaces
---
Diffs of the changes: (+45 -33)
SparcV8AsmPrinter.cpp | 4 +-
SparcV8ISelSimple.cpp | 72 +++++++++++++++++++++++++++--------------------
SparcV8TargetMachine.cpp | 2 -
3 files changed, 45 insertions(+), 33 deletions(-)
Index: llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.32 llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.33
--- llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp:1.32 Thu Apr 21 18:21:30 2005
+++ llvm/lib/Target/SparcV8/SparcV8AsmPrinter.cpp Fri Apr 22 13:06:01 2005
@@ -273,7 +273,7 @@
} else if (isa<ConstantAggregateZero> (CV)) {
unsigned size = TD.getTypeSize (CV->getType ());
for (unsigned i = 0; i < size; ++i)
- O << "\t.byte 0\n";
+ O << "\t.byte 0\n";
return;
}
@@ -362,7 +362,7 @@
<< "_" << I->getNumber () << ":\t! "
<< I->getBasicBlock ()->getName () << "\n";
for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
- II != E; ++II) {
+ II != E; ++II) {
// Print the assembly for the instruction.
O << "\t";
printMachineInstruction(II);
Index: llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.90 llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.91
--- llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp:1.90 Thu Apr 21 18:21:30 2005
+++ llvm/lib/Target/SparcV8/SparcV8ISelSimple.cpp Fri Apr 22 13:06:01 2005
@@ -876,23 +876,27 @@
if (getClassB (I.getOperand (i)->getType ()) < cLong) {
// Schlep it over into the incoming arg register
if (ArgOffset < 92) {
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else {
- BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
+ BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (ArgReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
if (ArgOffset < 92) {
- // Single-fp args are passed in integer registers; go through
- // memory to get them out of FP registers. (Bleh!)
- unsigned FltAlign = TM.getTargetData().getFloatAlignment();
- int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
- BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
+ // Single-fp args are passed in integer registers; go through
+ // memory to get them out of FP registers. (Bleh!)
+ unsigned FltAlign = TM.getTargetData().getFloatAlignment();
+ int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
+ BuildMI (BB, V8::STFri, 3).addFrameIndex(FI).addSImm(0).addReg(ArgReg);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
} else {
- BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
+ BuildMI (BB, V8::STFri, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (ArgReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cDouble) {
@@ -904,38 +908,46 @@
int FI = F->getFrameInfo()->CreateStackObject(8, DblAlign);
BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0).addReg (ArgReg);
if (ArgOffset < 92 && OAR != OAREnd) {
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (0);
} else {
unsigned TempReg = makeAnotherReg (Type::IntTy);
- BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
- BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
+ BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (0);
+ BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (TempReg);
}
ArgOffset += 4;
if (ArgOffset < 92 && OAR != OAREnd) {
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::LD, 2, *OAR++).addFrameIndex (FI).addSImm (4);
} else {
unsigned TempReg = makeAnotherReg (Type::IntTy);
- BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
- BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (TempReg);
+ BuildMI (BB, V8::LD, 2, TempReg).addFrameIndex (FI).addSImm (4);
+ BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (TempReg);
}
ArgOffset += 4;
} else if (getClassB (I.getOperand (i)->getType ()) == cLong) {
// do the first half...
if (ArgOffset < 92) {
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg);
} else {
- BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg);
+ BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (ArgReg);
}
ArgOffset += 4;
// ...then do the second half
if (ArgOffset < 92) {
- assert (OAR != OAREnd && "About to dereference past end of OutgoingArgRegs");
- BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
+ assert (OAR != OAREnd &&
+ "About to dereference past end of OutgoingArgRegs");
+ BuildMI (BB, V8::ORrr, 2, *OAR++).addReg (V8::G0).addReg (ArgReg+1);
} else {
- BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset).addReg (ArgReg+1);
+ BuildMI (BB, V8::ST, 3).addReg (V8::SP).addSImm (ArgOffset)
+ .addReg (ArgReg+1);
}
ArgOffset += 4;
} else {
@@ -1111,8 +1123,8 @@
///
void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
- Value *Src, User::op_iterator IdxBegin,
- User::op_iterator IdxEnd, unsigned TargetReg) {
+ Value *Src, User::op_iterator IdxBegin,
+ User::op_iterator IdxEnd, unsigned TargetReg) {
const TargetData &TD = TM.getTargetData ();
const Type *Ty = Src->getType ();
unsigned basePtrReg = getReg (Src, MBB, IP);
@@ -1776,13 +1788,13 @@
case Type::PointerTyID:
case Type::UIntTyID:
case Type::IntTyID:
- BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
+ BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
return;
case Type::ULongTyID:
case Type::LongTyID:
- BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
- BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
+ BuildMI (BB, V8::LD, 2, DestReg).addReg (VAList).addSImm (0);
+ BuildMI (BB, V8::LD, 2, DestReg+1).addReg (VAList).addSImm (4);
return;
case Type::DoubleTyID: {
Index: llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp
diff -u llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.26 llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.27
--- llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp:1.26 Thu Apr 21 18:21:30 2005
+++ llvm/lib/Target/SparcV8/SparcV8TargetMachine.cpp Fri Apr 22 13:06:01 2005
@@ -63,7 +63,7 @@
/// to implement a static compiler for this target.
///
bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
- std::ostream &Out) {
+ std::ostream &Out) {
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
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