[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC32ISelSimple.cpp PPC32RegisterInfo.cpp PPC64ISelPattern.cpp PPC64RegisterInfo.cpp

[Misha Brukman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.77 -> 1.78
PPC32ISelSimple.cpp updated: 1.140 -> 1.141
PPC32RegisterInfo.cpp updated: 1.11 -> 1.12
PPC64ISelPattern.cpp updated: 1.9 -> 1.10
PPC64RegisterInfo.cpp updated: 1.8 -> 1.9
---
Log message:

Convert tabs to spaces


---
Diffs of the changes:  (+11 -9)

 PPC32ISelPattern.cpp  |    7 ++++---
 PPC32ISelSimple.cpp   |    2 +-
 PPC32RegisterInfo.cpp |    2 +-
 PPC64ISelPattern.cpp  |    7 ++++---
 PPC64RegisterInfo.cpp |    2 +-
 5 files changed, 11 insertions(+), 9 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.77 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.78
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.77	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Apr 22 12:54:30 2005
@@ -263,8 +263,9 @@
 
 std::pair<SDOperand, SDOperand>
 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
-				 const Type *RetTy, bool isVarArg,
-         SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+                                 const Type *RetTy, bool isVarArg,
+                                 SDOperand Callee, ArgListTy &Args,
+                                 SelectionDAG &DAG) {
   // args_to_use will accumulate outgoing args for the ISD::CALL case in
   // SelectExpr to use to put the arguments in the appropriate registers.
   std::vector<SDOperand> args_to_use;
@@ -2366,7 +2367,7 @@
     case 3:
       assert(N.getOperand(1).getValueType() == MVT::i32 &&
              N.getOperand(2).getValueType() == MVT::i32 &&
-	           "Unknown two-register value!");
+             "Unknown two-register value!");
       Select(N.getOperand(0));
       Tmp1 = SelectExpr(N.getOperand(1));
       Tmp2 = SelectExpr(N.getOperand(2));


Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.140 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.141
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.140	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp	Fri Apr 22 12:54:30 2005
@@ -1306,7 +1306,7 @@
         }
       } // switch
       return;
-  	}
+    }
   }
   unsigned PPCOpcode = getPPCOpcodeForSetCCOpcode(Opcode);
 


Index: llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.11 llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.12
--- llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp:1.11	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC32RegisterInfo.cpp	Fri Apr 22 12:54:30 2005
@@ -50,7 +50,7 @@
 
 static const TargetRegisterClass *getClass(unsigned SrcReg) {
   if (PPC32::FPRCRegisterClass->contains(SrcReg))
-  	return PPC32::FPRCRegisterClass;
+    return PPC32::FPRCRegisterClass;
   assert(PPC32::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
   return PPC32::GPRCRegisterClass;
 }


Index: llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.9 llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.10
--- llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp:1.9	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC64ISelPattern.cpp	Fri Apr 22 12:54:30 2005
@@ -218,8 +218,9 @@
 
 std::pair<SDOperand, SDOperand>
 PPC64TargetLowering::LowerCallTo(SDOperand Chain,
-				 const Type *RetTy, bool isVarArg,
-         SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
+                                 const Type *RetTy, bool isVarArg,
+                                 SDOperand Callee, ArgListTy &Args,
+                                 SelectionDAG &DAG) {
   // args_to_use will accumulate outgoing args for the ISD::CALL case in
   // SelectExpr to use to put the arguments in the appropriate registers.
   std::vector<SDOperand> args_to_use;
@@ -1519,7 +1520,7 @@
     case 3:
       assert(N.getOperand(1).getValueType() == MVT::i32 &&
              N.getOperand(2).getValueType() == MVT::i32 &&
-	           "Unknown two-register value!");
+             "Unknown two-register value!");
       Select(N.getOperand(0));
       Tmp1 = SelectExpr(N.getOperand(1));
       Tmp2 = SelectExpr(N.getOperand(2));


Index: llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp
diff -u llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.8 llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.9
--- llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp:1.8	Thu Apr 21 18:20:02 2005
+++ llvm/lib/Target/PowerPC/PPC64RegisterInfo.cpp	Fri Apr 22 12:54:30 2005
@@ -50,7 +50,7 @@
 
 static const TargetRegisterClass *getClass(unsigned SrcReg) {
   if (PPC64::FPRCRegisterClass->contains(SrcReg))
-  	return PPC64::FPRCRegisterClass;
+    return PPC64::FPRCRegisterClass;
   assert(PPC64::GPRCRegisterClass->contains(SrcReg) && "Reg not FPR or GPR");
   return PPC64::GPRCRegisterClass;
 }