[llvm-commits] CVS: llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h IGNode.cpp IGNode.h InterferenceGraph.cpp InterferenceGraph.h LiveRange.h LiveRangeInfo.cpp LiveRangeInfo.h PhyRegAlloc.cpp PhyRegAlloc.h RegAllocCommon.h RegClass.cpp RegClass.h
Misha Brukman
brukman at cs.uiuc.edu
Thu Apr 21 16:30:25 PDT 2005
Changes in directory llvm/lib/Target/SparcV9/RegAlloc:
AllocInfo.h updated: 1.8 -> 1.9
IGNode.cpp updated: 1.12 -> 1.13
IGNode.h updated: 1.20 -> 1.21
InterferenceGraph.cpp updated: 1.22 -> 1.23
InterferenceGraph.h updated: 1.7 -> 1.8
LiveRange.h updated: 1.29 -> 1.30
LiveRangeInfo.cpp updated: 1.58 -> 1.59
LiveRangeInfo.h updated: 1.26 -> 1.27
PhyRegAlloc.cpp updated: 1.166 -> 1.167
PhyRegAlloc.h updated: 1.69 -> 1.70
RegAllocCommon.h updated: 1.12 -> 1.13
RegClass.cpp updated: 1.31 -> 1.32
RegClass.h updated: 1.23 -> 1.24
---
Log message:
Remove trailing whitespace
---
Diffs of the changes: (+372 -372)
AllocInfo.h | 10 -
IGNode.cpp | 14 +-
IGNode.h | 22 +--
InterferenceGraph.cpp | 72 +++++-----
InterferenceGraph.h | 20 +--
LiveRange.h | 24 +--
LiveRangeInfo.cpp | 80 ++++++------
LiveRangeInfo.h | 28 ++--
PhyRegAlloc.cpp | 328 +++++++++++++++++++++++++-------------------------
PhyRegAlloc.h | 38 ++---
RegAllocCommon.h | 8 -
RegClass.cpp | 72 +++++-----
RegClass.h | 28 ++--
13 files changed, 372 insertions(+), 372 deletions(-)
Index: llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.8 llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.9
--- llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h:1.8 Tue May 25 15:43:47 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/AllocInfo.h Thu Apr 21 18:30:13 2005
@@ -1,10 +1,10 @@
//===-- AllocInfo.h - Store info about regalloc decisions -------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This header file contains the data structure used to save the state
@@ -35,7 +35,7 @@
AllocInfo (int Inst_, int Op_, AllocStateTy State_, int Place_) :
Instruction(Inst_), Operand(Op_), AllocState(State_), Placement(Place_) { }
- /// AllocInfo constructor -- Default constructor creates an invalid AllocInfo
+ /// AllocInfo constructor -- Default constructor creates an invalid AllocInfo
/// (presumably to be replaced with something meaningful later).
///
AllocInfo () :
@@ -71,8 +71,8 @@
///
bool operator== (const AllocInfo &X) const {
return (X.AllocState == AllocState) && (X.Placement == Placement);
- }
- bool operator!= (const AllocInfo &X) const { return !(*this == X); }
+ }
+ bool operator!= (const AllocInfo &X) const { return !(*this == X); }
/// Returns a human-readable string representation of the AllocState member.
///
Index: llvm/lib/Target/SparcV9/RegAlloc/IGNode.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/IGNode.cpp:1.12 llvm/lib/Target/SparcV9/RegAlloc/IGNode.cpp:1.13
--- llvm/lib/Target/SparcV9/RegAlloc/IGNode.cpp:1.12 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/IGNode.cpp Thu Apr 21 18:30:14 2005
@@ -1,15 +1,15 @@
//===-- IGNode.cpp --------------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements an Interference graph node for coloring-based register
// allocation.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
@@ -19,11 +19,11 @@
namespace llvm {
//-----------------------------------------------------------------------------
-// Sets this IGNode on stack and reduce the degree of neighbors
+// Sets this IGNode on stack and reduce the degree of neighbors
//-----------------------------------------------------------------------------
void IGNode::pushOnStack() {
- OnStack = true;
+ OnStack = true;
int neighs = AdjList.size();
if (neighs < 0) {
@@ -34,7 +34,7 @@
for (int i=0; i < neighs; i++)
AdjList[i]->decCurDegree();
}
-
+
//-----------------------------------------------------------------------------
// Deletes an adjacency node. IGNodes are deleted when coalescing merges
// two IGNodes together.
Index: llvm/lib/Target/SparcV9/RegAlloc/IGNode.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.20 llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.21
--- llvm/lib/Target/SparcV9/RegAlloc/IGNode.h:1.20 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/IGNode.h Thu Apr 21 18:30:14 2005
@@ -1,16 +1,16 @@
//===-- IGNode.h - Represent a node in an interference graph ----*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file represents a node in an interference graph.
+// This file represents a node in an interference graph.
//
// For efficiency, the AdjList is updated only once - ie. we can add but not
-// remove nodes from AdjList.
+// remove nodes from AdjList.
//
// The removal of nodes from IG is simulated by decrementing the CurDegree.
// If this node is put on stack (that is removed from IG), the CurDegree of all
@@ -44,15 +44,15 @@
//----------------------------------------------------------------------------
class IGNode {
- const unsigned Index; // index within IGNodeList
+ const unsigned Index; // index within IGNodeList
bool OnStack; // this has been pushed on to stack for coloring
std::vector<IGNode *> AdjList;// adjacency list for this live range
- int CurDegree;
+ int CurDegree;
//
// set by InterferenceGraph::setCurDegreeOfIGNodes() after calculating
// all adjacency lists.
- // Decremented when a neighbor is pushed on to the stack.
+ // Decremented when a neighbor is pushed on to the stack.
// After that, never incremented/set again nor used.
LiveRange *const ParentLR;
@@ -68,15 +68,15 @@
// adjLists must be updated only once. However, the CurDegree can be changed
//
- inline void addAdjIGNode(IGNode *AdjNode) { AdjList.push_back(AdjNode); }
+ inline void addAdjIGNode(IGNode *AdjNode) { AdjList.push_back(AdjNode); }
- inline IGNode *getAdjIGNode(unsigned ind) const
+ inline IGNode *getAdjIGNode(unsigned ind) const
{ assert ( ind < AdjList.size()); return AdjList[ind]; }
// delete a node in AdjList - node must be in the list
// should not be called often
//
- void delAdjIGNode(const IGNode *Node);
+ void delAdjIGNode(const IGNode *Node);
inline unsigned getNumOfNeighbors() const { return AdjList.size(); }
@@ -87,7 +87,7 @@
// remove form IG and pushes on to stack (reduce the degree of neighbors)
//
- void pushOnStack();
+ void pushOnStack();
// CurDegree is the effective number of neighbors when neighbors are
// pushed on to the stack during the coloring phase. Must be called
Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.22 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.23
--- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp:1.22 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.cpp Thu Apr 21 18:30:14 2005
@@ -1,14 +1,14 @@
//===-- InterferenceGraph.cpp ---------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Interference graph for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
@@ -28,12 +28,12 @@
//-----------------------------------------------------------------------------
// Constructor: Records the RegClass and initalizes IGNodeList.
-// The matrix is NOT yet created by the constructor. Call createGraph()
+// The matrix is NOT yet created by the constructor. Call createGraph()
// to create it after adding all IGNodes to the IGNodeList.
//-----------------------------------------------------------------------------
InterferenceGraph::InterferenceGraph(RegClass *const RC) : RegCl(RC) {
- IG = NULL;
- Size = 0;
+ IG = NULL;
+ Size = 0;
if( DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "Interference graph created!\n";
}
@@ -58,15 +58,15 @@
// Creates (dynamically allocates) the bit matrix necessary to hold the
// interference graph.
//-----------------------------------------------------------------------------
-void InterferenceGraph::createGraph()
-{
+void InterferenceGraph::createGraph()
+{
Size = IGNodeList.size();
- IG = new char*[Size];
+ IG = new char*[Size];
for( unsigned int r=0; r < Size; ++r)
IG[r] = new char[Size];
// init IG matrix
- for(unsigned int i=0; i < Size; i++)
+ for(unsigned int i=0; i < Size; i++)
for(unsigned int j=0; j < Size; j++)
IG[i][j] = 0;
}
@@ -89,27 +89,27 @@
//-----------------------------------------------------------------------------
void InterferenceGraph::setInterference(const LiveRange *const LR1,
const LiveRange *const LR2 ) {
- assert(LR1 != LR2);
+ assert(LR1 != LR2);
IGNode *IGNode1 = LR1->getUserIGNode();
IGNode *IGNode2 = LR2->getUserIGNode();
- assertIGNode(this, IGNode1);
+ assertIGNode(this, IGNode1);
assertIGNode(this, IGNode2);
-
+
unsigned row = IGNode1->getIndex();
unsigned col = IGNode2->getIndex();
char *val;
- if( DEBUG_RA >= RA_DEBUG_Interference)
- std::cerr << "setting intf for: [" << row << "][" << col << "]\n";
+ if( DEBUG_RA >= RA_DEBUG_Interference)
+ std::cerr << "setting intf for: [" << row << "][" << col << "]\n";
- ( row > col) ? val = &IG[row][col]: val = &IG[col][row];
+ ( row > col) ? val = &IG[row][col]: val = &IG[col][row];
if( ! (*val) ) { // if this interf is not previously set
- *val = 1; // add edges between nodes
- IGNode1->addAdjIGNode( IGNode2 );
+ *val = 1; // add edges between nodes
+ IGNode1->addAdjIGNode( IGNode2 );
IGNode2->addAdjIGNode( IGNode1 );
}
@@ -122,17 +122,17 @@
unsigned InterferenceGraph::getInterference(const LiveRange *const LR1,
const LiveRange *const LR2) const {
assert(LR1 != LR2);
- assertIGNode(this, LR1->getUserIGNode());
+ assertIGNode(this, LR1->getUserIGNode());
assertIGNode(this, LR2->getUserIGNode());
const unsigned int row = LR1->getUserIGNode()->getIndex();
const unsigned int col = LR2->getUserIGNode()->getIndex();
- char ret;
+ char ret;
if (row > col)
ret = IG[row][col];
- else
- ret = IG[col][row];
+ else
+ ret = IG[col][row];
return ret;
}
@@ -141,11 +141,11 @@
//----------------------------------------------------------------------------
// Merge 2 IGNodes. The neighbors of the SrcNode will be added to the DestNode.
// Then the IGNode2L will be deleted. Necessary for coalescing.
-// IMPORTANT: The live ranges are NOT merged by this method. Use
+// IMPORTANT: The live ranges are NOT merged by this method. Use
// LiveRangeInfo::unionAndUpdateLRs for that purpose.
//----------------------------------------------------------------------------
-void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *LR1,
+void InterferenceGraph::mergeIGNodesOfLRs(const LiveRange *LR1,
LiveRange *LR2) {
assert( LR1 != LR2); // cannot merge the same live range
@@ -165,31 +165,31 @@
// for all neighs of SrcNode
- for(unsigned i=0; i < SrcDegree; i++) {
- IGNode *NeighNode = SrcNode->getAdjIGNode(i);
+ for(unsigned i=0; i < SrcDegree; i++) {
+ IGNode *NeighNode = SrcNode->getAdjIGNode(i);
LiveRange *const LROfNeigh = NeighNode->getParentLR();
// delete edge between src and neigh - even neigh == dest
- NeighNode->delAdjIGNode(SrcNode);
+ NeighNode->delAdjIGNode(SrcNode);
// set the matrix posn to 0 betn src and neigh - even neigh == dest
const unsigned NInd = NeighNode->getIndex();
- ( SrcInd > NInd) ? (IG[SrcInd][NInd]=0) : (IG[NInd][SrcInd]=0) ;
+ ( SrcInd > NInd) ? (IG[SrcInd][NInd]=0) : (IG[NInd][SrcInd]=0) ;
- if( LR1 != LROfNeigh) { // if the neigh != dest
-
+ if( LR1 != LROfNeigh) { // if the neigh != dest
+
// add edge betwn Dest and Neigh - if there is no current edge
- setInterference(LR1, LROfNeigh );
+ setInterference(LR1, LROfNeigh );
}
-
+
}
IGNodeList[ SrcInd ] = NULL;
// SrcNode is no longer necessary - LR2 must be deleted by the caller
- delete( SrcNode );
+ delete( SrcNode );
}
@@ -216,10 +216,10 @@
//--------------------- debugging (Printing) methods -----------------------
//----------------------------------------------------------------------------
-// Print the IGnodes
+// Print the IGnodes
//----------------------------------------------------------------------------
void InterferenceGraph::printIG() const {
- for(unsigned i=0; i < Size; i++) {
+ for(unsigned i=0; i < Size; i++) {
const IGNode *const Node = IGNodeList[i];
if(Node) {
std::cerr << " [" << i << "] ";
Index: llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.7 llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.8
--- llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h:1.7 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/InterferenceGraph.h Thu Apr 21 18:30:14 2005
@@ -1,10 +1,10 @@
//===-- InterferenceGraph.h - Interference graph for register coloring -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
/* Title: InterferenceGraph.h -*- C++ -*-
@@ -12,17 +12,17 @@
Date: July 20, 01
Purpose: Interference Graph used for register coloring.
- Notes:
- Adj Info is stored in the lower trangular matrix (i.e., row > col )
+ Notes:
+ Adj Info is stored in the lower trangular matrix (i.e., row > col )
This class must be used in the following way:
* Construct class
* call addLRToIG as many times to add ALL LRs to this IG
* call createGraph to create the actual matrix
- * Then setInterference, getInterference, mergeIGNodesOfLRs can be
+ * Then setInterference, getInterference, mergeIGNodesOfLRs can be
called as desired to modify the graph.
- * Once the modifications to the graph are over, call
+ * Once the modifications to the graph are over, call
setCurDegreeOfIGNodes() before pushing IGNodes on to stack for coloring.
*/
@@ -42,9 +42,9 @@
unsigned int Size; // size of a side of the IG
RegClass *const RegCl; // RegCl contains this IG
std::vector<IGNode *> IGNodeList; // a list of all IGNodes in a reg class
-
+
public:
- // the matrix is not yet created by the constructor. Call createGraph()
+ // the matrix is not yet created by the constructor. Call createGraph()
// to create it after adding all IGNodes to the IGNodeList
InterferenceGraph(RegClass *RC);
~InterferenceGraph();
@@ -61,8 +61,8 @@
void mergeIGNodesOfLRs(const LiveRange *LR1, LiveRange *LR2);
- std::vector<IGNode *> &getIGNodeList() { return IGNodeList; }
- const std::vector<IGNode *> &getIGNodeList() const { return IGNodeList; }
+ std::vector<IGNode *> &getIGNodeList() { return IGNodeList; }
+ const std::vector<IGNode *> &getIGNodeList() const { return IGNodeList; }
void setCurDegreeOfIGNodes();
Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.29 llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.30
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h:1.29 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRange.h Thu Apr 21 18:30:14 2005
@@ -1,10 +1,10 @@
//===-- LiveRange.h - Store info about a live range -------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Implements a live range using a SetVector of Value *s. We keep only
@@ -34,7 +34,7 @@
ValueContainerType MyValues; // Values in this LiveRange
RegClass *MyRegClass; // register class (e.g., int, FP) for this LR
- /// doesSpanAcrossCalls - Does this live range span across calls?
+ /// doesSpanAcrossCalls - Does this live range span across calls?
/// This information is used by graph coloring algo to avoid allocating
/// volatile colors to live ranges that span across calls (since they have to
/// be saved/restored)
@@ -56,7 +56,7 @@
/// this live range is not available before graph coloring (e.g., it
/// can be allocated to another live range which interferes with
/// this)
- ///
+ ///
bool CanUseSuggestedCol;
/// SpilledStackOffsetFromFP - If this LR is spilled, its stack
@@ -83,7 +83,7 @@
void insert(iterator b, iterator e) { MyValues.insert (b, e); }
LiveRange() {
- Color = SuggestedColor = -1; // not yet colored
+ Color = SuggestedColor = -1; // not yet colored
mustSpill = false;
MyRegClass = 0;
UserIGNode = 0;
@@ -99,21 +99,21 @@
unsigned getRegClassID() const;
bool hasColor() const { return Color != -1; }
-
+
unsigned getColor() const { assert(Color != -1); return (unsigned)Color; }
void setColor(unsigned Col) { Color = (int)Col; }
- inline void setCallInterference() {
+ inline void setCallInterference() {
doesSpanAcrossCalls = 1;
}
- inline void clearCallInterference() {
+ inline void clearCallInterference() {
doesSpanAcrossCalls = 0;
}
- inline bool isCallInterference() const {
- return doesSpanAcrossCalls == 1;
- }
+ inline bool isCallInterference() const {
+ return doesSpanAcrossCalls == 1;
+ }
inline void markForSpill() { mustSpill = true; }
@@ -150,7 +150,7 @@
inline const Type *getType() const {
return (*begin())->getType(); // set's don't have a front
}
-
+
inline void setSuggestedColor(int Col) {
if (SuggestedColor == -1)
SuggestedColor = Col;
Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.58 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.59
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp:1.58 Thu Mar 17 09:37:20 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.cpp Thu Apr 21 18:30:14 2005
@@ -1,14 +1,14 @@
//===-- LiveRangeInfo.cpp -------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Live range construction for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
@@ -35,8 +35,8 @@
LiveRangeInfo::~LiveRangeInfo() {
- for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
- MI != LiveRangeMap.end(); ++MI) {
+ for (LiveRangeMapType::iterator MI = LiveRangeMap.begin();
+ MI != LiveRangeMap.end(); ++MI) {
if (MI->first && MI->second) {
LiveRange *LR = MI->second;
@@ -48,7 +48,7 @@
for (LiveRange::iterator LI = LR->begin(); LI != LR->end(); ++LI)
LiveRangeMap[*LI] = 0;
-
+
delete LR;
}
}
@@ -70,14 +70,14 @@
for(LiveRange::iterator L2It = L2->begin(); L2It != L2->end(); ++L2It) {
L1->insert(*L2It); // add the var in L2 to L1
- LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
- //to L1
+ LiveRangeMap[*L2It] = L1; // now the elements in L2 should map
+ //to L1
}
-
+
// set call interference for L1 from L2
if (L2->isCallInterference())
L1->setCallInterference();
-
+
// add the spill costs
L1->addSpillCost(L2->getSpillCost());
@@ -90,7 +90,7 @@
// must have the same color.
if (L2->hasSuggestedColor())
L1->setSuggestedColor(L2->getSuggestedColor());
-
+
delete L2; // delete L2 as it is no longer needed
}
@@ -103,7 +103,7 @@
LiveRange*
LiveRangeInfo::createNewLiveRange(const Value* Def, bool isCC /* = false*/)
-{
+{
LiveRange* DefRange = new LiveRange(); // Create a new live range,
DefRange->insert(Def); // add Def to it,
LiveRangeMap[Def] = DefRange; // and update the map.
@@ -123,11 +123,11 @@
LiveRange*
LiveRangeInfo::createOrAddToLiveRange(const Value* Def, bool isCC /* = false*/)
-{
+{
LiveRange *DefRange = LiveRangeMap[Def];
// check if the LR is already there (because of multiple defs)
- if (!DefRange) {
+ if (!DefRange) {
DefRange = createNewLiveRange(Def, isCC);
} else { // live range already exists
DefRange->insert(Def); // add the operand to the range
@@ -140,13 +140,13 @@
//---------------------------------------------------------------------------
-// Method for constructing all live ranges in a function. It creates live
+// Method for constructing all live ranges in a function. It creates live
// ranges for all values defined in the instruction stream. Also, it
// creates live ranges for all incoming arguments of the function.
//---------------------------------------------------------------------------
-void LiveRangeInfo::constructLiveRanges() {
+void LiveRangeInfo::constructLiveRanges() {
- if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "Constructing Live Ranges ...\n";
// first find the live ranges for all incoming args of the function since
@@ -154,14 +154,14 @@
for (Function::const_arg_iterator AI = Meth->arg_begin(); AI != Meth->arg_end(); ++AI)
createNewLiveRange(AI, /*isCC*/ false);
- // Now suggest hardware registers for these function args
+ // Now suggest hardware registers for these function args
MRI.suggestRegs4MethodArgs(Meth, *this);
- // Now create LRs for machine instructions. A new LR will be created
+ // Now create LRs for machine instructions. A new LR will be created
// only for defs in the machine instr since, we assume that all Values are
// defined before they are used. However, there can be multiple defs for
// the same Value in machine instructions.
- //
+ //
// Also, find CALL and RETURN instructions, which need extra work.
//
MachineFunction &MF = MachineFunction::get(Meth);
@@ -170,21 +170,21 @@
// iterate over all the machine instructions in BB
for(MachineBasicBlock::iterator MInstIterator = MBB.begin();
- MInstIterator != MBB.end(); ++MInstIterator) {
- MachineInstr *MInst = MInstIterator;
+ MInstIterator != MBB.end(); ++MInstIterator) {
+ MachineInstr *MInst = MInstIterator;
// If the machine instruction is a call/return instruction, add it to
// CallRetInstrList for processing its args, ret value, and ret addr.
- //
+ //
if(TM.getInstrInfo()->isReturn(MInst->getOpcode()) ||
TM.getInstrInfo()->isCall(MInst->getOpcode()))
- CallRetInstrList.push_back(MInst);
-
+ CallRetInstrList.push_back(MInst);
+
// iterate over explicit MI operands and create a new LR
// for each operand that is defined by the instruction
for (MachineInstr::val_op_iterator OpI = MInst->begin(),
OpE = MInst->end(); OpI != OpE; ++OpI)
- if (OpI.isDef()) {
+ if (OpI.isDef()) {
const Value *Def = *OpI;
bool isCC = (OpI.getMachineOperand().getType()
== MachineOperand::MO_CCRegister);
@@ -201,7 +201,7 @@
// iterate over implicit MI operands and create a new LR
// for each operand that is defined by the instruction
- for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
+ for (unsigned i = 0; i < MInst->getNumImplicitRefs(); ++i)
if (MInst->getImplicitOp(i).isDef()) {
const Value *Def = MInst->getImplicitRef(i);
LiveRange* LR = createOrAddToLiveRange(Def, /*isCC*/ false);
@@ -222,10 +222,10 @@
// Now we have to suggest clors for call and return arg live ranges.
// Also, if there are implicit defs (e.g., retun value of a call inst)
// they must be added to the live range list
- //
+ //
suggestRegs4CallRets();
- if( DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if( DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "Initial Live Ranges constructed!\n";
}
@@ -235,7 +235,7 @@
// (e.g., for outgoing call args), suggesting of colors for such live
// ranges is done using target specific function. Those functions are called
// from this function. The target specific methods must:
-// 1) suggest colors for call and return args.
+// 1) suggest colors for call and return args.
// 2) create new LRs for implicit defs in machine instructions
//---------------------------------------------------------------------------
void LiveRangeInfo::suggestRegs4CallRets() {
@@ -248,7 +248,7 @@
MRI.suggestReg4RetValue(MInst, *this);
else if (TM.getInstrInfo()->isCall(OpCode))
MRI.suggestRegs4CallArgs(MInst, *this);
- else
+ else
assert( 0 && "Non call/ret instr in CallRetInstrList" );
}
}
@@ -268,7 +268,7 @@
if the def and op do not interfere //i.e., not simultaneously live
if (degree(LR of def) + degree(LR of op)) <= # avail regs
if both LRs do not have suggested colors
- merge2IGNodes(def, op) // i.e., merge 2 LRs
+ merge2IGNodes(def, op) // i.e., merge 2 LRs
*/
//---------------------------------------------------------------------------
@@ -276,7 +276,7 @@
// Checks if live range LR interferes with any node assigned or suggested to
// be assigned the specified color
-//
+//
inline bool InterferesWithColor(const LiveRange& LR, unsigned color) {
IGNode* lrNode = LR.getUserIGNode();
for (unsigned n=0, NN = lrNode->getNumOfNeighbors(); n < NN; n++) {
@@ -295,7 +295,7 @@
// (but if the colors are the same, it is definitely safe to coalesce)
// (3) LR1 has color and LR2 interferes with any LR that has the same color
// (4) LR2 has color and LR1 interferes with any LR that has the same color
-//
+//
inline bool InterfsPreventCoalescing(const LiveRange& LROfDef,
const LiveRange& LROfUse) {
// (4) if they have different suggested colors, cannot coalesce
@@ -318,9 +318,9 @@
}
-void LiveRangeInfo::coalesceLRs()
+void LiveRangeInfo::coalesceLRs()
{
- if(DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if(DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "\nCoalescing LRs ...\n";
MachineFunction &MF = MachineFunction::get(Meth);
@@ -364,7 +364,7 @@
if (!RCOfDef->getInterference(LROfDef, LROfUse) ) {
unsigned CombinedDegree =
- LROfDef->getUserIGNode()->getNumOfNeighbors() +
+ LROfDef->getUserIGNode()->getNumOfNeighbors() +
LROfUse->getUserIGNode()->getNumOfNeighbors();
if (CombinedDegree > RCOfDef->getNumOfAvailRegs()) {
@@ -390,7 +390,7 @@
} // for all machine instructions
} // for all BBs
- if (DEBUG_RA >= RA_DEBUG_LiveRanges)
+ if (DEBUG_RA >= RA_DEBUG_LiveRanges)
std::cerr << "\nCoalescing Done!\n";
}
@@ -402,7 +402,7 @@
std::cerr << "\nPrinting Live Ranges from Hash Map:\n";
for( ; HMI != LiveRangeMap.end(); ++HMI) {
if (HMI->first && HMI->second) {
- std::cerr << " Value* " << RAV(HMI->first) << "\t: ";
+ std::cerr << " Value* " << RAV(HMI->first) << "\t: ";
if (IGNode* igNode = HMI->second->getUserIGNode())
std::cerr << "LR# " << igNode->getIndex();
else
Index: llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.26 llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.27
--- llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h:1.26 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h Thu Apr 21 18:30:14 2005
@@ -1,18 +1,18 @@
//===-- LiveRangeInfo.h - Track all LiveRanges for a Function ----*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// This file contains the class LiveRangeInfo which constructs and keeps
+// This file contains the class LiveRangeInfo which constructs and keeps
// the LiveRangeMap which contains all the live ranges used in a method.
//
-// Assumptions:
+// Assumptions:
//
-// All variables (llvm Values) are defined before they are used. However, a
+// All variables (llvm Values) are defined before they are used. However, a
// constant may not be defined in the machine instruction stream if it can be
// used as an immediate value within a machine instruction. However, register
// allocation does not have to worry about immediate constants since they
@@ -45,16 +45,16 @@
//----------------------------------------------------------------------------
// Class LiveRangeInfo
//
-// Constructs and keeps the LiveRangeMap which contains all the live
+// Constructs and keeps the LiveRangeMap which contains all the live
// ranges used in a method. Also contain methods to coalesce live ranges.
//----------------------------------------------------------------------------
class LiveRangeInfo {
const Function *const Meth; // Func for which live range info is held
- LiveRangeMapType LiveRangeMap; // A map from Value * to LiveRange * to
+ LiveRangeMapType LiveRangeMap; // A map from Value * to LiveRange * to
// record all live ranges in a method
// created by constructLiveRanges
-
+
const TargetMachine& TM; // target machine description
std::vector<RegClass *> & RegClassList;// vector containing register classess
@@ -76,8 +76,8 @@
void suggestRegs4CallRets ();
public:
-
- LiveRangeInfo(const Function *F,
+
+ LiveRangeInfo(const Function *F,
const TargetMachine& tm,
std::vector<RegClass *> & RCList);
@@ -89,10 +89,10 @@
// Main entry point for live range construction
//
void constructLiveRanges();
-
+
/// return the common live range map for this method
///
- inline const LiveRangeMapType *getLiveRangeMap() const
+ inline const LiveRangeMapType *getLiveRangeMap() const
{ return &LiveRangeMap; }
/// Method used to get the live range containing a Value.
@@ -109,7 +109,7 @@
/// Method for coalescing live ranges. Called only after interference info
/// is calculated.
///
- void coalesceLRs();
+ void coalesceLRs();
/// debugging method to print the live ranges
///
@@ -118,4 +118,4 @@
} // End llvm namespace
-#endif
+#endif
Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.166 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.167
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp:1.166 Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp Thu Apr 21 18:30:14 2005
@@ -1,12 +1,12 @@
//===-- PhyRegAlloc.cpp ---------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Traditional graph-coloring global register allocator currently used
// by the SPARC back-end.
//
@@ -17,7 +17,7 @@
// NOTE 2: This register allocator can save its state in a global
// variable in the module it's working on. This feature is not
// thread-safe; if you have doubts, leave it turned off.
-//
+//
//===----------------------------------------------------------------------===//
#include "AllocInfo.h"
@@ -93,13 +93,13 @@
void PhyRegAlloc::createIGNodeListsAndIGs() {
if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "Creating LR lists ...\n";
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
for (; HMI != HMIEnd ; ++HMI ) {
- if (HMI->first) {
+ if (HMI->first) {
LiveRange *L = HMI->second; // get the LiveRange
- if (!L) {
+ if (!L) {
if (DEBUG_RA && !isa<ConstantIntegral> (HMI->first))
std::cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
<< RAV(HMI->first) << "****\n";
@@ -107,16 +107,16 @@
}
// if the Value * is not null, and LR is not yet written to the IGNodeList
- if (!(L->getUserIGNode()) ) {
+ if (!(L->getUserIGNode()) ) {
RegClass *const RC = // RegClass of first value in the LR
RegClassList[ L->getRegClassID() ];
RC->addLRToIG(L); // add this LR to an IG
}
}
}
-
+
// init RegClassList
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
RegClassList[rc]->createInterferenceGraph();
if (DEBUG_RA >= RA_DEBUG_LiveRanges) std::cerr << "LRLists Created!\n";
@@ -133,12 +133,12 @@
ValueSet::const_iterator LIt = LVSet->begin();
// get the live range of instruction
- const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
+ const LiveRange *const LROfDef = LRI->getLiveRangeForValue( Def );
IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
assert( IGNodeOfDef );
- RegClass *const RCOfDef = LROfDef->getRegClass();
+ RegClass *const RCOfDef = LROfDef->getRegClass();
// for each live var in live variable set
for ( ; LIt != LVSet->end(); ++LIt) {
@@ -149,22 +149,22 @@
// get the live range corresponding to live var
LiveRange *LROfVar = LRI->getLiveRangeForValue(*LIt);
- // LROfVar can be null if it is a const since a const
+ // LROfVar can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
if (LROfVar)
if (LROfDef != LROfVar) // do not set interf for same LR
if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
- RCOfDef->setInterference( LROfDef, LROfVar);
+ RCOfDef->setInterference( LROfDef, LROfVar);
}
}
-/// For a call instruction, this method sets the CallInterference flag in
+/// For a call instruction, this method sets the CallInterference flag in
/// the LR of each variable live in the Live Variable Set live after the
/// call instruction (except the return value of the call instruction - since
/// the return value does not interfere with that call itself).
///
-void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
+void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
const ValueSet *LVSetAft) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n For call inst: " << *MInst;
@@ -174,11 +174,11 @@
LIt != LEnd; ++LIt) {
// get the live range corresponding to live var
- LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
+ LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
- if (LR) {
+ if (LR) {
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "\n\tLR after Call: " << *LR << "\n";
LR->setCallInterference();
@@ -193,7 +193,7 @@
// of the call is live in this set - but it does not interfere with call
// (i.e., we can allocate a volatile register to the return value)
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
-
+
if (const Value *RetVal = argDesc->getReturnValue()) {
LiveRange *RetValLR = LRI->getLiveRangeForValue( RetVal );
assert( RetValLR && "No LR for RetValue of call");
@@ -205,7 +205,7 @@
if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
LiveRange *AddrValLR = LRI->getLiveRangeForValue( AddrVal );
// LR can be null if the function pointer is a constant.
- if (AddrValLR)
+ if (AddrValLR)
AddrValLR->setCallInterference();
}
}
@@ -225,7 +225,7 @@
const MachineBasicBlock &MBB = *BBI;
const BasicBlock *BB = MBB.getBasicBlock();
- // find the 10^(loop_depth) of this BB
+ // find the 10^(loop_depth) of this BB
BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
// get the iterator for machine instructions
@@ -256,19 +256,19 @@
// Calculate the spill cost of each live range
LiveRange *LR = LRI->getLiveRangeForValue(*OpI);
if (LR) LR->addSpillCost(BBLoopDepthCost);
- }
+ }
// Also add interference for any implicit definitions in a machine
// instr (currently, only calls have this).
unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
- for (unsigned z=0; z < NumOfImpRefs; z++)
+ for (unsigned z=0; z < NumOfImpRefs; z++)
if (MInst->getImplicitOp(z).isDef())
addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
} // for all machine instructions in BB
} // for all BBs in function
- // add interferences for function arguments. Since there are no explicit
+ // add interferences for function arguments. Since there are no explicit
// defs in the function for args, we have to add them manually
- addInterferencesForArgs();
+ addInterferencesForArgs();
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << "Interference graphs calculated!\n";
@@ -284,19 +284,19 @@
// iterate over MI operands to find defs
for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
ItE = MInst->end(); It1 != ItE; ++It1) {
- const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
+ const LiveRange *LROfOp1 = LRI->getLiveRangeForValue(*It1);
assert((LROfOp1 || It1.isDef()) && "No LR for Def in PSEUDO insruction");
MachineInstr::const_val_op_iterator It2 = It1;
for (++It2; It2 != ItE; ++It2) {
- const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
+ const LiveRange *LROfOp2 = LRI->getLiveRangeForValue(*It2);
if (LROfOp2) {
- RegClass *RCOfOp1 = LROfOp1->getRegClass();
- RegClass *RCOfOp2 = LROfOp2->getRegClass();
-
- if (RCOfOp1 == RCOfOp2 ){
- RCOfOp1->setInterference( LROfOp1, LROfOp2 );
+ RegClass *RCOfOp1 = LROfOp1->getRegClass();
+ RegClass *RCOfOp2 = LROfOp2->getRegClass();
+
+ if (RCOfOp1 == RCOfOp2 ){
+ RCOfOp1->setInterference( LROfOp1, LROfOp2 );
setInterf = true;
}
} // if Op2 has a LR
@@ -308,19 +308,19 @@
std::cerr << *MInst;
assert(0 && "Interf not set for pseudo instr with > 2 operands" );
}
-}
+}
/// Add interferences for incoming arguments to a function.
///
void PhyRegAlloc::addInterferencesForArgs() {
// get the InSet of root BB
- const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
+ const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
for (Function::const_arg_iterator AI = Fn->arg_begin(); AI != Fn->arg_end(); ++AI) {
- // add interferences between args and LVars at start
+ // add interferences between args and LVars at start
addInterference(AI, &InSet, false);
-
+
if (DEBUG_RA >= RA_DEBUG_Interference)
std::cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
}
@@ -353,7 +353,7 @@
const std::string& msg) {
if (!IBef.empty()) {
MachineInstr* OrigMI = MII;
- std::vector<MachineInstr *>::iterator AdIt;
+ std::vector<MachineInstr *>::iterator AdIt;
for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt) {
if (DEBUG_RA) {
if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
@@ -371,7 +371,7 @@
const std::string& msg) {
if (!IAft.empty()) {
MachineInstr* OrigMI = MII;
- std::vector<MachineInstr *>::iterator AdIt;
+ std::vector<MachineInstr *>::iterator AdIt;
for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt ) {
if (DEBUG_RA) {
if (OrigMI) std::cerr << "For MInst:\n " << *OrigMI;
@@ -395,7 +395,7 @@
// will need to know which registers are already used by this instr'n.
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister) {
const Value *const Val = Op.getVRegValue();
if (const LiveRange* LR = LRI->getLiveRangeForValue(Val)) {
@@ -425,7 +425,7 @@
unsigned Opcode = MInst->getOpcode();
// Reset tmp stack positions so they can be reused for each machine instr.
- MF->getInfo<SparcV9FunctionInfo>()->popAllTempValues();
+ MF->getInfo<SparcV9FunctionInfo>()->popAllTempValues();
// Mark the operands for which regs have been allocated.
bool instrNeedsSpills = markAllocatedRegs(MII);
@@ -453,7 +453,7 @@
if (instrNeedsSpills)
for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
MachineOperand& Op = MInst->getOperand(OpNum);
- if (Op.getType() == MachineOperand::MO_VirtualRegister ||
+ if (Op.getType() == MachineOperand::MO_VirtualRegister ||
Op.getType() == MachineOperand::MO_CCRegister) {
const Value* Val = Op.getVRegValue();
if (const LiveRange *LR = LRI->getLiveRangeForValue(Val))
@@ -476,13 +476,13 @@
assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
"InstrsAfter should be unnecessary since we are just inserting at "
"the function entry point here.");
-
+
for (MachineFunction::iterator BBI = MF->begin(), BBE = MF->end();
BBI != BBE; ++BBI) {
MachineBasicBlock &MBB = *BBI;
// Iterate over all machine instructions in BB and mark operands with
- // their assigned registers or insert spill code, as appropriate.
+ // their assigned registers or insert spill code, as appropriate.
// Also, fix operands of call/return instructions.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (MII->getOpcode() != V9::PHI)
@@ -495,19 +495,19 @@
// move any existing instructions out of the delay slot so that the
// instructions can go into the delay slot. This only supports the
// case that #instrsAfter <= #delay slots.
- //
+ //
// (2) If any instruction in the delay slot needs
// instructions inserted, move it out of the delay slot and before the
// branch because putting code before or after it would be VERY BAD!
- //
+ //
// If the annul bit of the branch is set, neither of these is legal!
// If so, we need to handle spill differently but annulling is not yet used.
for (MachineBasicBlock::iterator MII = MBB.begin(); MII != MBB.end(); ++MII)
if (unsigned delaySlots =
- TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
+ TM.getInstrInfo()->getNumDelaySlots(MII->getOpcode())) {
MachineBasicBlock::iterator DelaySlotMI = next(MII);
assert(DelaySlotMI != MBB.end() && "no instruction for delay slot");
-
+
// Check the 2 conditions above:
// (1) Does a branch need instructions added after it?
// (2) O/w does delay slot instr. need instrns before or after?
@@ -550,7 +550,7 @@
// Finally iterate over all instructions in BB and insert before/after
for (MachineBasicBlock::iterator MII=MBB.begin(); MII != MBB.end(); ++MII) {
- MachineInstr *MInst = MII;
+ MachineInstr *MInst = MII;
// do not process Phis
if (MInst->getOpcode() == V9::PHI)
@@ -579,12 +579,12 @@
assert(instrsSeen.count(CallAI.InstrnsBefore[i]) == 0 &&
"Duplicate machine instruction in InstrnsBefore!");
instrsSeen.insert(CallAI.InstrnsBefore[i]);
- }
+ }
for (int i = 0, N = CallAI.InstrnsAfter.size(); i < N; ++i) {
assert(instrsSeen.count(CallAI.InstrnsAfter[i]) == 0 &&
"Duplicate machine instruction in InstrnsBefore/After!");
instrsSeen.insert(CallAI.InstrnsAfter[i]);
- }
+ }
#endif
// Now add the instructions before/after this MI.
@@ -592,7 +592,7 @@
// as close as possible to an instruction (see above insertCode4Spill)
if (! CallAI.InstrnsBefore.empty())
PrependInstructions(CallAI.InstrnsBefore, MBB, MII,"");
-
+
if (! CallAI.InstrnsAfter.empty())
AppendInstructions(CallAI.InstrnsAfter, MBB, MII,"");
@@ -609,7 +609,7 @@
/// instruction. Then it uses this register temporarily to accommodate the
/// spilled value.
///
-void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
+void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB,
const unsigned OpNum) {
@@ -645,26 +645,26 @@
#endif
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
std::vector<MachineInstr*> MIBef, MIAft;
std::vector<MachineInstr*> AdIMid;
-
+
// Choose a register to hold the spilled value, if one was not preallocated.
// This may insert code before and after MInst to free up the value. If so,
// this code should be first/last in the spill sequence before/after MInst.
int TmpRegU=(LR->hasColor()
? MRI.getUnifiedRegNum(LR->getRegClassID(),LR->getColor())
: getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef,MIAft));
-
+
// Set the operand first so that it this register does not get used
// as a scratch register for later calls to getUsableUniRegAtMI below
MInst->SetRegForOperand(OpNum, TmpRegU);
-
+
// get the added instructions for this instruction
AddedInstrns &AI = AddedInstrMap[MInst];
// We may need a scratch register to copy the spilled value to/from memory.
- // This may itself have to insert code to free up a scratch register.
+ // This may itself have to insert code to free up a scratch register.
// Any such code should go before (after) the spill code for a load (store).
// The scratch reg is not marked as used because it is only used
// for the copy and not used across MInst.
@@ -675,35 +675,35 @@
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (isUse) {
// for a USE, we have to load the value of LR from stack to a TmpReg
// and use the TmpReg as one operand of instruction
-
+
// actual loading instruction(s)
MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU,
RegType, scratchReg);
-
+
// the actual load should be after the instructions to free up TmpRegU
MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
AdIMid.clear();
}
-
+
if (isDef) { // if this is a Def
// for a DEF, we have to store the value produced by this instruction
// on the stack position allocated for this LR
-
+
// actual storing instruction(s)
MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff,
RegType, scratchReg);
-
+
MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
} // if !DEF
-
+
// Finally, insert the entire spill code sequences before/after MInst
AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
-
+
if (DEBUG_RA) {
std::cerr << "\nFor Inst:\n " << *MInst;
std::cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
@@ -721,15 +721,15 @@
void
PhyRegAlloc::insertCallerSavingCode(std::vector<MachineInstr*> &instrnsBefore,
std::vector<MachineInstr*> &instrnsAfter,
- MachineInstr *CallMI,
+ MachineInstr *CallMI,
const BasicBlock *BB) {
assert(TM.getInstrInfo()->isCall(CallMI->getOpcode()));
-
+
// hash set to record which registers were saved/restored
hash_set<unsigned> PushedRegSet;
CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
-
+
// if the call is to a instrumentation function, do not insert save and
// restore instructions the instrumentation function takes care of save
// restore for volatile regs.
@@ -770,9 +770,9 @@
// get the live range corresponding to live var
LiveRange *const LR = LRI->getLiveRangeForValue(*LIt);
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
- if (LR) {
+ if (LR) {
if (! LR->isMarkedForSpill()) {
assert(LR->hasColor() && "LR is neither spilled nor colored?");
unsigned RCID = LR->getRegClassID();
@@ -785,10 +785,10 @@
if (isLLVMFirstTrigger && !MRI.modifiedByCall(RCID, Color))
continue;
- // if the value is in both LV sets (i.e., live before and after
+ // if the value is in both LV sets (i.e., live before and after
// the call machine instruction)
unsigned Reg = MRI.getUnifiedRegNum(RCID, Color);
-
+
// if we haven't already pushed this register...
if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
unsigned RegType = MRI.getRegTypeForLR(LR);
@@ -798,11 +798,11 @@
// call instruction
int StackOff =
MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
//---- Insert code for pushing the reg on stack ----------
-
+
std::vector<MachineInstr*> AdIBef, AdIAft;
-
+
// We may need a scratch register to copy the saved value
// to/from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go before
@@ -819,22 +819,22 @@
CallMI, AdIBef, AdIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (AdIBef.size() > 0)
instrnsBefore.insert(instrnsBefore.end(),
AdIBef.begin(), AdIBef.end());
-
+
MRI.cpReg2MemMI(instrnsBefore, Reg, MRI.getFramePointer(),
StackOff, RegType, scratchReg);
-
+
if (AdIAft.size() > 0)
instrnsBefore.insert(instrnsBefore.end(),
AdIAft.begin(), AdIAft.end());
-
+
//---- Insert code for popping the reg from the stack ----------
AdIBef.clear();
AdIAft.clear();
-
+
// We may need a scratch register to copy the saved value
// from memory. This may itself have to insert code to
// free up a scratch register. Any such code should go
@@ -847,20 +847,20 @@
CallMI, AdIBef, AdIAft);
assert(scratchReg != MRI.getInvalidRegNum());
}
-
+
if (AdIBef.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIBef.begin(), AdIBef.end());
-
+
MRI.cpMem2RegMI(instrnsAfter, MRI.getFramePointer(), StackOff,
Reg, RegType, scratchReg);
-
+
if (AdIAft.size() > 0)
instrnsAfter.insert(instrnsAfter.end(),
AdIAft.begin(), AdIAft.end());
-
+
PushedRegSet.insert(Reg);
-
+
if(DEBUG_RA) {
std::cerr << "\nFor call inst:" << *CallMI;
std::cerr << " -inserted caller saving instrs: Before:\n\t ";
@@ -869,7 +869,7 @@
std::cerr << " -and After:\n\t ";
for_each(instrnsAfter.begin(), instrnsAfter.end(),
std::mem_fun(&MachineInstr::dump));
- }
+ }
} // if not already pushed
} // if LR has a volatile color
} // if LR has color
@@ -885,28 +885,28 @@
///
int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
const ValueSet *LVSetBef,
- MachineInstr *MInst,
+ MachineInstr *MInst,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft) {
RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
-
+
int RegU = getUnusedUniRegAtMI(RC, RegType, MInst, LVSetBef);
-
+
if (RegU == -1) {
// we couldn't find an unused register. Generate code to free up a reg by
// saving it on stack and restoring after the instruction
-
+
int TmpOff = MF->getInfo<SparcV9FunctionInfo>()->pushTempValue(MRI.getSpilledRegSize(RegType));
-
+
RegU = getUniRegNotUsedByThisInst(RC, RegType, MInst);
-
+
// Check if we need a scratch register to copy this register to memory.
int scratchRegType = -1;
if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType)) {
int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
MInst, MIBef, MIAft);
assert(scratchReg != MRI.getInvalidRegNum());
-
+
// We may as well hold the value in the scratch register instead
// of copying it to memory and back. But we have to mark the
// register as used by this instruction, so it does not get used
@@ -919,7 +919,7 @@
MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
}
}
-
+
return RegU;
}
@@ -945,9 +945,9 @@
// for each live var in live variable set after machine inst
for ( ; LIt != LVSetBef->end(); ++LIt) {
// Get the live range corresponding to live var, and its RegClass
- LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
+ LiveRange *const LRofLV = LRI->getLiveRangeForValue(*LIt );
- // LR can be null if it is a const since a const
+ // LR can be null if it is a const since a const
// doesn't have a dominating def - see Assumptions above
if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor())
RC->markColorsUsed(LRofLV->getColor(),
@@ -970,7 +970,7 @@
/// Return the unified register number of a register in class RC which is not
/// used by any operands of MInst.
///
-int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
+int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
const int RegType,
const MachineInstr *MInst) {
RC->clearColorsUsed();
@@ -1024,7 +1024,7 @@
// If there are implicit references, mark their allocated regs as well
for (unsigned z=0; z < MI->getNumImplicitRefs(); z++)
if (const LiveRange*
- LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
+ LRofImpRef = LRI->getLiveRangeForValue(MI->getImplicitRef(z)))
if (LRofImpRef->hasColor())
// this implicit reference is in a LR that received a color
RC->markColorsUsed(LRofImpRef->getColor(),
@@ -1075,11 +1075,11 @@
///
void PhyRegAlloc::markUnusableSugColors()
{
- LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
- LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
+ LiveRangeMapType::const_iterator HMI = (LRI->getLiveRangeMap())->begin();
+ LiveRangeMapType::const_iterator HMIEnd = (LRI->getLiveRangeMap())->end();
for (; HMI != HMIEnd ; ++HMI ) {
- if (HMI->first) {
+ if (HMI->first) {
LiveRange *L = HMI->second; // get the LiveRange
if (L && L->hasSuggestedColor ())
L->setSuggestedColorUsable
@@ -1097,8 +1097,8 @@
void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
if (DEBUG_RA) std::cerr << "\nSetting LR stack offsets for spills...\n";
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap()->begin();
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap()->end();
for ( ; HMI != HMIEnd ; ++HMI) {
if (HMI->first && HMI->second) {
@@ -1117,26 +1117,26 @@
void PhyRegAlloc::saveStateForValue (std::vector<AllocInfo> &state,
const Value *V, int Insn, int Opnd) {
- LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
- LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
- AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
- int Placement = -1;
- if ((HMI != HMIEnd) && HMI->second) {
- LiveRange *L = HMI->second;
- assert ((L->hasColor () || L->isMarkedForSpill ())
- && "Live range exists but not colored or spilled");
- if (L->hasColor ()) {
- AllocState = AllocInfo::Allocated;
- Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
- L->getColor ());
- } else if (L->isMarkedForSpill ()) {
- AllocState = AllocInfo::Spilled;
- assert (L->hasSpillOffset ()
- && "Live range marked for spill but has no spill offset");
- Placement = L->getSpillOffFromFP ();
- }
- }
- state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
+ LiveRangeMapType::const_iterator HMI = LRI->getLiveRangeMap ()->find (V);
+ LiveRangeMapType::const_iterator HMIEnd = LRI->getLiveRangeMap ()->end ();
+ AllocInfo::AllocStateTy AllocState = AllocInfo::NotAllocated;
+ int Placement = -1;
+ if ((HMI != HMIEnd) && HMI->second) {
+ LiveRange *L = HMI->second;
+ assert ((L->hasColor () || L->isMarkedForSpill ())
+ && "Live range exists but not colored or spilled");
+ if (L->hasColor ()) {
+ AllocState = AllocInfo::Allocated;
+ Placement = MRI.getUnifiedRegNum (L->getRegClassID (),
+ L->getColor ());
+ } else if (L->isMarkedForSpill ()) {
+ AllocState = AllocInfo::Spilled;
+ assert (L->hasSpillOffset ()
+ && "Live range marked for spill but has no spill offset");
+ Placement = L->getSpillOffFromFP ();
+ }
+ }
+ state.push_back (AllocInfo (Insn, Opnd, AllocState, Placement));
}
@@ -1173,7 +1173,7 @@
}
-bool PhyRegAlloc::doFinalization (Module &M) {
+bool PhyRegAlloc::doFinalization (Module &M) {
if (SaveRegAllocState) finishSavingState (M);
return false;
}
@@ -1263,38 +1263,38 @@
/// Allocate registers for the machine code previously generated for F using
/// the graph-coloring algorithm.
///
-bool PhyRegAlloc::runOnFunction (Function &F) {
- if (DEBUG_RA)
- std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
-
- Fn = &F;
- MF = &MachineFunction::get (Fn);
- LVI = &getAnalysis<FunctionLiveVarInfo> ();
- LRI = new LiveRangeInfo (Fn, TM, RegClassList);
- LoopDepthCalc = &getAnalysis<LoopInfo> ();
-
- // Create each RegClass for the target machine and add it to the
+bool PhyRegAlloc::runOnFunction (Function &F) {
+ if (DEBUG_RA)
+ std::cerr << "\n********* Function "<< F.getName () << " ***********\n";
+
+ Fn = &F;
+ MF = &MachineFunction::get (Fn);
+ LVI = &getAnalysis<FunctionLiveVarInfo> ();
+ LRI = new LiveRangeInfo (Fn, TM, RegClassList);
+ LoopDepthCalc = &getAnalysis<LoopInfo> ();
+
+ // Create each RegClass for the target machine and add it to the
// RegClassList. This must be done before calling constructLiveRanges().
- for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
- RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
- MRI.getMachineRegClass(rc)));
-
+ for (unsigned rc = 0; rc != NumOfRegClasses; ++rc)
+ RegClassList.push_back (new RegClass (Fn, TM.getRegInfo(),
+ MRI.getMachineRegClass(rc)));
+
LRI->constructLiveRanges(); // create LR info
if (DEBUG_RA >= RA_DEBUG_LiveRanges)
LRI->printLiveRanges();
-
+
createIGNodeListsAndIGs(); // create IGNode list and IGs
buildInterferenceGraphs(); // build IGs in all reg classes
-
+
if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
// print all LRs in all reg classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->printIGNodeList();
-
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->printIGNodeList();
+
// print IGs in all register classes
- for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->printIG();
+ for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->printIG();
}
LRI->coalesceLRs(); // coalesce all live ranges
@@ -1303,7 +1303,7 @@
// print all LRs in all reg classes
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
RegClassList[rc]->printIGNodeList();
-
+
// print IGs in all register classes
for (unsigned rc=0; rc < NumOfRegClasses; rc++)
RegClassList[rc]->printIG();
@@ -1312,11 +1312,11 @@
// mark un-usable suggested color before graph coloring algorithm.
// When this is done, the graph coloring algo will not reserve
// suggested color unnecessarily - they can be used by another LR
- markUnusableSugColors();
+ markUnusableSugColors();
// color all register classes using the graph coloring algo
- for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
- RegClassList[rc]->colorAllRegs();
+ for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
+ RegClassList[rc]->colorAllRegs();
// After graph coloring, if some LRs did not receive a color (i.e, spilled)
// a position for such spilled LRs
@@ -1336,7 +1336,7 @@
// Now update the machine code with register names and add any additional
// code inserted by the register allocator to the instruction stream.
- updateMachineCode();
+ updateMachineCode();
if (SaveRegAllocState && !SaveStateToModule)
finishSavingState (const_cast<Module&> (*Fn->getParent ()));
@@ -1345,19 +1345,19 @@
std::cerr << "\n**** Machine Code After Register Allocation:\n\n";
MF->dump();
}
-
- // Tear down temporary data structures
- for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
- delete RegClassList[rc];
- RegClassList.clear ();
- AddedInstrMap.clear ();
- OperandsColoredMap.clear ();
- ScratchRegsUsed.clear ();
- AddedInstrAtEntry.clear ();
+
+ // Tear down temporary data structures
+ for (unsigned rc = 0; rc < NumOfRegClasses; ++rc)
+ delete RegClassList[rc];
+ RegClassList.clear ();
+ AddedInstrMap.clear ();
+ OperandsColoredMap.clear ();
+ ScratchRegsUsed.clear ();
+ AddedInstrAtEntry.clear ();
delete LRI;
- if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
+ if (DEBUG_RA) std::cerr << "\nRegister allocation complete!\n";
return false; // Function was not modified
-}
+}
} // End llvm namespace
Index: llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.69 llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.70
--- llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h:1.69 Fri Aug 6 14:11:43 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h Thu Apr 21 18:30:14 2005
@@ -1,16 +1,16 @@
//===-- PhyRegAlloc.h - Graph Coloring Register Allocator -------*- c++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This is the main entry point for register allocation.
//
// Notes:
-// * RegisterClasses: Each RegClass accepts a
+// * RegisterClasses: Each RegClass accepts a
// TargetRegClass which contains machine specific info about that register
// class. The code in the RegClass is machine independent and they use
// access functions in the TargetRegClass object passed into it to get
@@ -27,7 +27,7 @@
#include "LiveRangeInfo.h"
#include "llvm/Pass.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
-#include "llvm/Target/TargetMachine.h"
+#include "llvm/Target/TargetMachine.h"
#include "../SparcV9RegInfo.h"
#include <map>
@@ -42,9 +42,9 @@
//----------------------------------------------------------------------------
// Class AddedInstrns:
-// When register allocator inserts new instructions in to the existing
+// When register allocator inserts new instructions in to the existing
// instruction stream, it does NOT directly modify the instruction stream.
-// Rather, it creates an object of AddedInstrns and stick it in the
+// Rather, it creates an object of AddedInstrns and stick it in the
// AddedInstrMap for an existing instruction. This class contains two vectors
// to store such instructions added before and after an existing instruction.
//----------------------------------------------------------------------------
@@ -66,8 +66,8 @@
const TargetMachine &TM; // target machine
const Function *Fn; // name of the function we work on
MachineFunction *MF; // descriptor for method's native code
- FunctionLiveVarInfo *LVI; // LV information for this method
- // (already computed for BBs)
+ FunctionLiveVarInfo *LVI; // LV information for this method
+ // (already computed for BBs)
LiveRangeInfo *LRI; // LR info (will be computed)
const SparcV9RegInfo &MRI; // Machine Register information
const unsigned NumOfRegClasses; // recorded here for efficiency
@@ -76,7 +76,7 @@
// updated according to their assigned colors. This is only used in
// assertion checking (debug builds).
std::map<const MachineInstr *, bool> OperandsColoredMap;
-
+
// AddedInstrMap - Used to store instrns added in this phase
std::map<const MachineInstr *, AddedInstrns> AddedInstrMap;
@@ -85,7 +85,7 @@
ScratchRegsUsedTy ScratchRegsUsed;
AddedInstrns AddedInstrAtEntry; // to store instrns added at entry
- const LoopInfo *LoopDepthCalc; // to calculate loop depths
+ const LoopInfo *LoopDepthCalc; // to calculate loop depths
PhyRegAlloc(const PhyRegAlloc&); // DO NOT IMPLEMENT
void operator=(const PhyRegAlloc&); // DO NOT IMPLEMENT
@@ -117,7 +117,7 @@
private:
SavedStateMapTy FnAllocState;
- void addInterference(const Value *Def, const ValueSet *LVSet,
+ void addInterference(const Value *Def, const ValueSet *LVSet,
bool isCallInst);
bool markAllocatedRegs(MachineInstr* MInst);
@@ -130,16 +130,16 @@
void saveState();
void finishSavingState(Module &M);
- void setCallInterferences(const MachineInstr *MI,
+ void setCallInterferences(const MachineInstr *MI,
const ValueSet *LVSetAft);
- void move2DelayedInstr(const MachineInstr *OrigMI,
+ void move2DelayedInstr(const MachineInstr *OrigMI,
const MachineInstr *DelayedMI);
void markUnusableSugColors();
void allocateStackSpace4SpilledLRs();
- void insertCode4SpilledLR(const LiveRange *LR,
+ void insertCode4SpilledLR(const LiveRange *LR,
MachineBasicBlock::iterator& MII,
MachineBasicBlock &MBB, unsigned OpNum);
@@ -161,17 +161,17 @@
MachineInstr *MI,
std::vector<MachineInstr*>& MIBef,
std::vector<MachineInstr*>& MIAft);
-
- /// Callback method used to find unused registers.
+
+ /// Callback method used to find unused registers.
/// LVSetBef is the live variable set to search for an unused register.
/// If it is not specified, the LV set before the current MI is used.
/// This is sufficient as long as no new copy instructions are generated
/// to copy the free register to memory.
- ///
+ ///
int getUnusedUniRegAtMI(RegClass *RC, int RegType,
const MachineInstr *MI,
const ValueSet *LVSetBef = 0);
-
+
void setRelRegsUsedByThisInst(RegClass *RC, int RegType,
const MachineInstr *MI);
Index: llvm/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h:1.12 llvm/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h:1.13
--- llvm/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h:1.12 Tue Nov 11 16:41:33 2003
+++ llvm/lib/Target/SparcV9/RegAlloc/RegAllocCommon.h Thu Apr 21 18:30:14 2005
@@ -1,14 +1,14 @@
//===-- RegAllocCommon.h --------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Shared declarations for register allocation.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef REGALLOCCOMMON_H
Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp
diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.31 llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.32
--- llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp:1.31 Sun Jul 4 07:19:56 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.cpp Thu Apr 21 18:30:14 2005
@@ -1,14 +1,14 @@
//===-- RegClass.cpp -----------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// class RegClass for coloring-based register allocation for LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#include "IGNode.h"
@@ -20,10 +20,10 @@
namespace llvm {
//----------------------------------------------------------------------------
-// This constructor inits IG. The actual matrix is created by a call to
+// This constructor inits IG. The actual matrix is created by a call to
// createInterferenceGraph() above.
//----------------------------------------------------------------------------
-RegClass::RegClass(const Function *M,
+RegClass::RegClass(const Function *M,
const SparcV9RegInfo *_MRI_,
const TargetRegClassInfo *_MRC_)
: Meth(M), MRI(_MRI_), MRC(_MRC_),
@@ -47,10 +47,10 @@
// pre-color IGNodes
pushAllIGNodes(); // push all IG Nodes
- unsigned int StackSize = IGNodeStack.size();
+ unsigned int StackSize = IGNodeStack.size();
IGNode *CurIGNode;
// for all LRs on stack
- for (unsigned int IGN=0; IGN < StackSize; IGN++) {
+ for (unsigned int IGN=0; IGN < StackSize; IGN++) {
CurIGNode = IGNodeStack.top(); // pop the IGNode on top of stack
IGNodeStack.pop();
colorIGNode (CurIGNode); // color it
@@ -64,13 +64,13 @@
//----------------------------------------------------------------------------
void RegClass::pushAllIGNodes()
{
- bool NeedMoreSpills;
+ bool NeedMoreSpills;
IG.setCurDegreeOfIGNodes(); // calculate degree of IGNodes
// push non-constrained IGNodes
- bool PushedAll = pushUnconstrainedIGNodes();
+ bool PushedAll = pushUnconstrainedIGNodes();
if (DEBUG_RA >= RA_DEBUG_Coloring) {
std::cerr << " Puhsed all-unconstrained IGNodes. ";
@@ -82,22 +82,22 @@
return;
- // now, we have constrained nodes. So, push one of them (the one with min
- // spill cost) and try to push the others as unConstrained nodes.
+ // now, we have constrained nodes. So, push one of them (the one with min
+ // spill cost) and try to push the others as unConstrained nodes.
// Repeat this.
do {
//get node with min spill cost
- IGNode *IGNodeSpill = getIGNodeWithMinSpillCost();
+ IGNode *IGNodeSpill = getIGNodeWithMinSpillCost();
// push that node on to stack
IGNodeStack.push(IGNodeSpill);
- // set its OnStack flag and decrement degree of neighs
- IGNodeSpill->pushOnStack();
+ // set its OnStack flag and decrement degree of neighs
+ IGNodeSpill->pushOnStack();
// now push NON-constrained ones, if any
- NeedMoreSpills = !pushUnconstrainedIGNodes();
+ NeedMoreSpills = !pushUnconstrainedIGNodes();
if (DEBUG_RA >= RA_DEBUG_Coloring)
std::cerr << "\nConstrained IG Node found !@!" << IGNodeSpill->getIndex();
- } while(NeedMoreSpills); // repeat until we have pushed all
+ } while(NeedMoreSpills); // repeat until we have pushed all
}
@@ -105,26 +105,26 @@
//--------------------------------------------------------------------------
-// This method goes thru all IG nodes in the IGNodeList of an IG of a
+// This method goes thru all IG nodes in the IGNodeList of an IG of a
// register class and push any unconstrained IG node left (that is not
// already pushed)
//--------------------------------------------------------------------------
-bool RegClass::pushUnconstrainedIGNodes()
+bool RegClass::pushUnconstrainedIGNodes()
{
- // # of LRs for this reg class
- unsigned int IGNodeListSize = IG.getIGNodeList().size();
+ // # of LRs for this reg class
+ unsigned int IGNodeListSize = IG.getIGNodeList().size();
bool pushedall = true;
// a pass over IGNodeList
for (unsigned i =0; i < IGNodeListSize; i++) {
// get IGNode i from IGNodeList
- IGNode *IGNode = IG.getIGNodeList()[i];
+ IGNode *IGNode = IG.getIGNodeList()[i];
- if (!IGNode ) // can be null due to merging
+ if (!IGNode ) // can be null due to merging
continue;
-
+
// if already pushed on stack, continue. This can happen since this
// method can be called repeatedly until all constrained nodes are
// pushed
@@ -141,11 +141,11 @@
}
}
else pushedall = false; // we didn't push all live ranges
-
+
} // for
-
+
// returns true if we pushed all live ranges - else false
- return pushedall;
+ return pushedall;
}
@@ -154,7 +154,7 @@
// Get the IGNode with the minimum spill cost
//----------------------------------------------------------------------------
IGNode * RegClass::getIGNodeWithMinSpillCost() {
- unsigned int IGNodeListSize = IG.getIGNodeList().size();
+ unsigned int IGNodeListSize = IG.getIGNodeList().size();
double MinSpillCost = 0;
IGNode *MinCostIGNode = NULL;
bool isFirstNode = true;
@@ -163,14 +163,14 @@
// among all IGNodes that are not yet pushed on to the stack
for (unsigned int i =0; i < IGNodeListSize; i++) {
IGNode *IGNode = IG.getIGNodeList()[i];
-
+
if (!IGNode) // can be null due to merging
continue;
if (!IGNode->isOnStack()) {
double SpillCost = (double) IGNode->getParentLR()->getSpillCost() /
(double) (IGNode->getCurDegree() + 1);
-
+
if (isFirstNode) { // for the first IG node
MinSpillCost = SpillCost;
MinCostIGNode = IGNode;
@@ -181,7 +181,7 @@
}
}
}
-
+
assert (MinCostIGNode && "No IGNode to spill");
return MinCostIGNode;
}
@@ -192,7 +192,7 @@
//----------------------------------------------------------------------------
void RegClass::colorIGNode(IGNode *const Node) {
if (! Node->hasColor()) { // not colored as an arg etc.
-
+
// init all elements of to IsColorUsedAr false;
clearColorsUsed();
@@ -202,7 +202,7 @@
for (unsigned n=0; n < NumNeighbors; n++) {
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
-
+
// Don't use a color if it is in use by the neighbor,
// or is suggested for use by the neighbor,
// markColorsUsed() should be given the color and the reg type for
@@ -240,12 +240,12 @@
void RegClass::printIGNodeList() const {
std::cerr << "IG Nodes for Register Class " << RegClassID << ":" << "\n";
- IG.printIGNodeList();
+ IG.printIGNodeList();
}
-void RegClass::printIG() {
+void RegClass::printIG() {
std::cerr << "IG for Register Class " << RegClassID << ":" << "\n";
- IG.printIG();
+ IG.printIG();
}
} // End llvm namespace
Index: llvm/lib/Target/SparcV9/RegAlloc/RegClass.h
diff -u llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.23 llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.24
--- llvm/lib/Target/SparcV9/RegAlloc/RegClass.h:1.23 Wed Jun 2 21:45:09 2004
+++ llvm/lib/Target/SparcV9/RegAlloc/RegClass.h Thu Apr 21 18:30:14 2005
@@ -1,10 +1,10 @@
//===-- RegClass.h - Machine Independent register coloring ------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
/* Title: RegClass.h -*- C++ -*-
@@ -29,23 +29,23 @@
//-----------------------------------------------------------------------------
// Class RegClass
//
-// Implements a machine independent register class.
+// Implements a machine independent register class.
//
// This is the class that contains all data structures and common algos
-// for coloring a particular register class (e.g., int class, fp class).
-// This class is hardware independent. This class accepts a hardware
-// dependent description of machine registers (TargetRegInfo class) to
+// for coloring a particular register class (e.g., int class, fp class).
+// This class is hardware independent. This class accepts a hardware
+// dependent description of machine registers (TargetRegInfo class) to
// get hardware specific info and to color an individual IG node.
//
// This class contains the InterferenceGraph (IG).
-// Also it contains an IGNode stack that can be used for coloring.
+// Also it contains an IGNode stack that can be used for coloring.
// The class provides some easy access methods to the IG methods, since these
// methods are called thru a register class.
//
//-----------------------------------------------------------------------------
class RegClass {
const Function *const Meth; // Function we are working on
- const SparcV9RegInfo *MRI; // Machine register information
+ const SparcV9RegInfo *MRI; // Machine register information
const TargetRegClassInfo *const MRC; // Machine reg. class for this RegClass
const unsigned RegClassID; // my int ID
@@ -100,28 +100,28 @@
// main method called for coloring regs
//
- void colorAllRegs();
+ void colorAllRegs();
- inline unsigned getNumOfAvailRegs() const
+ inline unsigned getNumOfAvailRegs() const
{ return MRC->getNumOfAvailRegs(); }
// --- following methods are provided to access the IG contained within this
// ---- RegClass easilly.
- inline void addLRToIG(LiveRange *const LR)
+ inline void addLRToIG(LiveRange *const LR)
{ IG.addLRToIG(LR); }
inline void setInterference(const LiveRange *const LR1,
- const LiveRange *const LR2)
+ const LiveRange *const LR2)
{ IG.setInterference(LR1, LR2); }
inline unsigned getInterference(const LiveRange *const LR1,
- const LiveRange *const LR2) const
+ const LiveRange *const LR2) const
{ return IG.getInterference(LR1, LR2); }
inline void mergeIGNodesOfLRs(const LiveRange *const LR1,
- LiveRange *const LR2)
+ LiveRange *const LR2)
{ IG.mergeIGNodesOfLRs(LR1, LR2); }
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