[llvm-commits] CVS: llvm/lib/Target/SparcV9/MachineCodeForInstruction.h MachineFunctionInfo.h MachineInstrAnnot.h MappingInfo.h SparcV9BurgISel.h SparcV9CodeEmitter.h SparcV9FrameInfo.h SparcV9InstrForest.h SparcV9InstrInfo.h SparcV9Internals.h SparcV9JITInfo.h SparcV9RegClassInfo.h SparcV9RegInfo.h SparcV9RegisterInfo.h SparcV9Relocations.h SparcV9TargetMachine.h SparcV9TmpInstr.h DecomposeMultiDimRefs.cpp EmitBytecodeToAssembly.cpp InternalGlobalMapper.cpp MachineCodeForInstruction.cpp MachineFunctionInfo.cpp MappingInfo.cpp SparcV9AsmPrinter.cpp SparcV9BurgISel.cpp SparcV9CodeEmitter.cpp SparcV9FrameInfo.cpp SparcV9JITInfo.cpp SparcV9PeepholeOpts.cpp SparcV9PreSelection.cpp SparcV9PrologEpilogInserter.cpp SparcV9RegClassInfo.cpp SparcV9RegInfo.cpp SparcV9RegisterInfo.cpp SparcV9SchedInfo.cpp SparcV9StackSlots.cpp SparcV9TargetMachine.cpp SparcV9TmpInstr.cpp
Misha Brukman
brukman at cs.uiuc.edu
Thu Apr 21 16:25:54 PDT 2005
Changes in directory llvm/lib/Target/SparcV9:
MachineCodeForInstruction.h updated: 1.16 -> 1.17
MachineFunctionInfo.h updated: 1.9 -> 1.10
MachineInstrAnnot.h updated: 1.16 -> 1.17
MappingInfo.h updated: 1.10 -> 1.11
SparcV9BurgISel.h updated: 1.1 -> 1.2
SparcV9CodeEmitter.h updated: 1.19 -> 1.20
SparcV9FrameInfo.h updated: 1.8 -> 1.9
SparcV9InstrForest.h updated: 1.2 -> 1.3
SparcV9InstrInfo.h updated: 1.10 -> 1.11
SparcV9Internals.h updated: 1.119 -> 1.120
SparcV9JITInfo.h updated: 1.7 -> 1.8
SparcV9RegClassInfo.h updated: 1.28 -> 1.29
SparcV9RegInfo.h updated: 1.16 -> 1.17
SparcV9RegisterInfo.h updated: 1.6 -> 1.7
SparcV9Relocations.h updated: 1.1 -> 1.2
SparcV9TargetMachine.h updated: 1.11 -> 1.12
SparcV9TmpInstr.h updated: 1.3 -> 1.4
DecomposeMultiDimRefs.cpp updated: 1.2 -> 1.3
EmitBytecodeToAssembly.cpp updated: 1.15 -> 1.16
InternalGlobalMapper.cpp updated: 1.6 -> 1.7
MachineCodeForInstruction.cpp updated: 1.3 -> 1.4
MachineFunctionInfo.cpp updated: 1.2 -> 1.3
MappingInfo.cpp updated: 1.21 -> 1.22
SparcV9AsmPrinter.cpp updated: 1.126 -> 1.127
SparcV9BurgISel.cpp updated: 1.16 -> 1.17
SparcV9CodeEmitter.cpp updated: 1.79 -> 1.80
SparcV9FrameInfo.cpp updated: 1.7 -> 1.8
SparcV9JITInfo.cpp updated: 1.1 -> 1.2
SparcV9PeepholeOpts.cpp updated: 1.26 -> 1.27
SparcV9PreSelection.cpp updated: 1.42 -> 1.43
SparcV9PrologEpilogInserter.cpp updated: 1.47 -> 1.48
SparcV9RegClassInfo.cpp updated: 1.39 -> 1.40
SparcV9RegInfo.cpp updated: 1.139 -> 1.140
SparcV9RegisterInfo.cpp updated: 1.4 -> 1.5
SparcV9SchedInfo.cpp updated: 1.13 -> 1.14
SparcV9StackSlots.cpp updated: 1.14 -> 1.15
SparcV9TargetMachine.cpp updated: 1.134 -> 1.135
SparcV9TmpInstr.cpp updated: 1.4 -> 1.5
---
Log message:
Remove trailing whitespace
---
Diffs of the changes: (+957 -955)
DecomposeMultiDimRefs.cpp | 22 -
EmitBytecodeToAssembly.cpp | 22 -
InternalGlobalMapper.cpp | 6
MachineCodeForInstruction.cpp | 16
MachineCodeForInstruction.h | 18 -
MachineFunctionInfo.cpp | 30 -
MachineFunctionInfo.h | 28 -
MachineInstrAnnot.h | 30 -
MappingInfo.cpp | 28 -
MappingInfo.h | 4
SparcV9AsmPrinter.cpp | 72 ++--
SparcV9BurgISel.cpp | 720 ++++++++++++++++++++--------------------
SparcV9BurgISel.h | 6
SparcV9CodeEmitter.cpp | 28 -
SparcV9CodeEmitter.h | 20 -
SparcV9FrameInfo.cpp | 16
SparcV9FrameInfo.h | 14
SparcV9InstrForest.h | 12
SparcV9InstrInfo.h | 8
SparcV9Internals.h | 18 -
SparcV9JITInfo.cpp | 34 -
SparcV9JITInfo.h | 6
SparcV9PeepholeOpts.cpp | 18 -
SparcV9PreSelection.cpp | 30 -
SparcV9PrologEpilogInserter.cpp | 30 -
SparcV9RegClassInfo.cpp | 90 ++---
SparcV9RegClassInfo.h | 48 +-
SparcV9RegInfo.cpp | 194 +++++-----
SparcV9RegInfo.h | 70 +--
SparcV9RegisterInfo.cpp | 4
SparcV9RegisterInfo.h | 8
SparcV9Relocations.h | 4
SparcV9SchedInfo.cpp | 182 +++++-----
SparcV9StackSlots.cpp | 12
SparcV9TargetMachine.cpp | 40 +-
SparcV9TargetMachine.h | 8
SparcV9TmpInstr.cpp | 4
SparcV9TmpInstr.h | 12
38 files changed, 957 insertions(+), 955 deletions(-)
Index: llvm/lib/Target/SparcV9/MachineCodeForInstruction.h
diff -u llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.16 llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.17
--- llvm/lib/Target/SparcV9/MachineCodeForInstruction.h:1.16 Mon Aug 16 16:54:29 2004
+++ llvm/lib/Target/SparcV9/MachineCodeForInstruction.h Thu Apr 21 18:25:42 2005
@@ -1,28 +1,28 @@
//===-- MachineCodeForInstruction.h -----------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
-// FIXME: This file is SparcV9 specific. Do not rely on this class for new
+// FIXME: This file is SparcV9 specific. Do not rely on this class for new
// targets, it will go away in the future.
//
// Representation of the sequence of machine instructions created for a single
// VM instruction. Additionally records information about hidden and implicit
// values used by the machine instructions: about hidden values used by the
// machine instructions:
-//
+//
// "Temporary values" are intermediate values used in the machine instruction
// sequence, but not in the VM instruction Note that such values should be
// treated as pure SSA values with no interpretation of their operands (i.e., as
// a TmpInstruction object which actually represents such a value).
-//
+//
// (2) "Implicit uses" are values used in the VM instruction but not in
// the machine instruction sequence
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINECODE_FOR_INSTRUCTION_H
@@ -44,7 +44,7 @@
public:
MachineCodeForInstruction() : callArgsDesc(NULL) {}
~MachineCodeForInstruction();
-
+
static MachineCodeForInstruction &get(const Instruction *I);
static void destroy(const Instruction *I);
@@ -71,7 +71,7 @@
}
iterator erase(iterator where) { return Contents.erase(where); }
iterator erase(iterator s, iterator e) { return Contents.erase(s, e); }
-
+
// dropAllReferences() - This function drops all references within
// temporary (hidden) instructions created in implementing the original
@@ -82,7 +82,7 @@
const std::vector<Value*> &getTempValues() const { return tempVec; }
std::vector<Value*> &getTempValues() { return tempVec; }
-
+
MachineCodeForInstruction &addTemp(Value *tmp) {
tempVec.push_back(tmp);
return *this;
Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.h
diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.9 llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.10
--- llvm/lib/Target/SparcV9/MachineFunctionInfo.h:1.9 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/MachineFunctionInfo.h Thu Apr 21 18:25:42 2005
@@ -1,18 +1,18 @@
//===-- SparcV9FunctionInfo.h -----------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This class keeps track of information about the stack frame and about the
// per-function constant pool.
//
// FIXME: This class is completely SparcV9 specific. Do not use it for future
// targets. This file will be eliminated in future versions of LLVM.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINEFUNCTIONINFO_H
@@ -62,7 +62,7 @@
//
// Accessors for global information about generated code for a method.
- //
+ //
bool isCompiledAsLeafMethod() const { return compiledAsLeaf; }
unsigned getStaticStackSize() const { return staticStackSize; }
unsigned getAutomaticVarsSize() const { return automaticVarsSize; }
@@ -72,31 +72,31 @@
const hash_set<const Constant*> &getConstantPoolValues() const {
return constantsForConstPool;
}
-
+
//
// Modifiers used during code generation
- //
+ //
void initializeFrameLayout ();
-
+
void addToConstantPool (const Constant* constVal) {
constantsForConstPool.insert(constVal);
}
-
+
void markAsLeafMethod() { compiledAsLeaf = true; }
-
+
int computeOffsetforLocalVar (const Value* local,
unsigned& getPaddedSize,
unsigned sizeToUse = 0);
int allocateLocalVar (const Value* local,
unsigned sizeToUse = 0);
-
+
int allocateSpilledValue (const Type* type);
int pushTempValue (unsigned size);
void popAllTempValues ();
-
- void freezeSpillsArea () { spillsAreaFrozen = true; }
+
+ void freezeSpillsArea () { spillsAreaFrozen = true; }
void freezeAutomaticVarsArea () { automaticVarsAreaFrozen=true; }
-
+
private:
void incrementAutomaticVarsSize(int incr) {
automaticVarsSize+= incr;
Index: llvm/lib/Target/SparcV9/MachineInstrAnnot.h
diff -u llvm/lib/Target/SparcV9/MachineInstrAnnot.h:1.16 llvm/lib/Target/SparcV9/MachineInstrAnnot.h:1.17
--- llvm/lib/Target/SparcV9/MachineInstrAnnot.h:1.16 Wed Jun 2 21:45:09 2004
+++ llvm/lib/Target/SparcV9/MachineInstrAnnot.h Thu Apr 21 18:25:42 2005
@@ -1,14 +1,14 @@
//===-- MachineInstrAnnot.h -------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Annotations used to pass information between SparcV9 code generation phases.
-//
+//
//===----------------------------------------------------------------------===//
#ifndef MACHINEINSTRANNOT_H
@@ -28,29 +28,29 @@
static const unsigned char IntArgReg = 0x1;
static const unsigned char FPArgReg = 0x2;
static const unsigned char StackSlot = 0x4;
-
+
Value* argVal; // this argument
int argCopyReg; // register used for second copy of arg. when
// multiple copies must be passed in registers
unsigned char passingMethod; // flags recording passing methods
-
+
public:
// Constructors
CallArgInfo(Value* _argVal)
: argVal(_argVal), argCopyReg(SparcV9RegInfo::getInvalidRegNum()),
passingMethod(0x0) {}
-
+
CallArgInfo(const CallArgInfo& obj)
: argVal(obj.argVal), argCopyReg(obj.argCopyReg),
passingMethod(obj.passingMethod) {}
-
+
// Accessor methods
Value* getArgVal() { return argVal; }
int getArgCopy() { return argCopyReg; }
- bool usesIntArgReg() { return (bool) (passingMethod & IntArgReg);}
- bool usesFPArgReg() { return (bool) (passingMethod & FPArgReg); }
- bool usesStackSlot() { return (bool) (passingMethod & StackSlot);}
-
+ bool usesIntArgReg() { return (bool) (passingMethod & IntArgReg);}
+ bool usesFPArgReg() { return (bool) (passingMethod & FPArgReg); }
+ bool usesStackSlot() { return (bool) (passingMethod & StackSlot);}
+
// Modifier methods
void replaceArgVal(Value* newVal) { argVal = newVal; }
void setUseIntArgReg() { passingMethod |= IntArgReg; }
@@ -64,15 +64,15 @@
std::vector<CallArgInfo> argInfoVec; // Descriptor for each argument
CallInst* callInstr; // The call instruction == result value
- Value* funcPtr; // Pointer for indirect calls
+ Value* funcPtr; // Pointer for indirect calls
TmpInstruction* retAddrReg; // Tmp value for return address reg.
bool isVarArgs; // Is this a varargs call?
bool noPrototype; // Is this a call with no prototype?
-
+
public:
CallArgsDescriptor(CallInst* _callInstr, TmpInstruction* _retAddrReg,
bool _isVarArgs, bool _noPrototype);
-
+
// Accessor methods to retrieve information about the call
// Note that operands are numbered 1..#CallArgs
unsigned int getNumArgs() const { return argInfoVec.size(); }
@@ -86,7 +86,7 @@
bool hasNoPrototype() const { return noPrototype; }
// Mechanism to get the descriptor for a CALL MachineInstr.
- //
+ //
static CallArgsDescriptor *get(const MachineInstr* MI);
};
Index: llvm/lib/Target/SparcV9/MappingInfo.h
diff -u llvm/lib/Target/SparcV9/MappingInfo.h:1.10 llvm/lib/Target/SparcV9/MappingInfo.h:1.11
--- llvm/lib/Target/SparcV9/MappingInfo.h:1.10 Sun Sep 19 23:46:39 2004
+++ llvm/lib/Target/SparcV9/MappingInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- lib/Target/SparcV9/MappingInfo.h -------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Data structures to support the Reoptimizer's Instruction-to-MachineInstr
Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.h
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.h:1.1 llvm/lib/Target/SparcV9/SparcV9BurgISel.h:1.2
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.h:1.1 Wed Aug 4 02:28:51 2004
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9BurgISel.h ---------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Global functions exposed by the BURG-based instruction selector
@@ -41,7 +41,7 @@
/// or a GlobalValue, viz., the constant address of a global variable or
/// function. The generated instructions are returned in `mvec'. Any temp.
/// registers (TmpInstruction) created are recorded in mcfi.
-///
+///
void CreateCodeToLoadConst (const TargetMachine &target, Function *F,
Value *val, Instruction *dest, std::vector<MachineInstr*> &mvec,
MachineCodeForInstruction &mcfi);
Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.h
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.h:1.19 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.h:1.20
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.h:1.19 Mon Nov 22 14:25:10 2004
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.h Thu Apr 21 18:25:42 2005
@@ -1,12 +1,12 @@
//===-- SparcV9CodeEmitter.h ------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Target-specific portions of the machine code emitter for the SparcV9.
// This class interfaces with the JIT's Emitter in order to turn MachineInstrs
// into words of binary machine code. Its code is partially generated by
@@ -52,31 +52,31 @@
/// emitWord - writes out the given 32-bit value to memory at the current PC.
///
void emitWord(unsigned Val);
-
+
/// getBinaryCodeForInstr - This function, generated by the
/// CodeEmitterGenerator using TableGen, produces the binary encoding for
/// machine instructions.
///
unsigned getBinaryCodeForInstr(MachineInstr &MI);
-private:
- /// getMachineOpValue -
+private:
+ /// getMachineOpValue -
///
int64_t getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
- /// emitBasicBlock -
+ /// emitBasicBlock -
///
void emitBasicBlock(MachineBasicBlock &MBB);
- /// getValueBit -
+ /// getValueBit -
///
unsigned getValueBit(int64_t Val, unsigned bit);
- /// getGlobalAddress -
+ /// getGlobalAddress -
///
void* getGlobalAddress(GlobalValue *V, MachineInstr &MI,
bool isPCRelative);
- /// emitFarCall -
+ /// emitFarCall -
///
unsigned getRealRegNum(unsigned fakeReg, MachineInstr &MI);
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.8 llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.9
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.h:1.8 Thu Aug 12 13:36:53 2004
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9FrameInfo.h - Define TargetFrameInfo for SparcV9 -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Interface to stack frame layout info for the UltraSPARC.
@@ -25,7 +25,7 @@
public:
SparcV9FrameInfo(const TargetMachine &TM)
: TargetFrameInfo(StackGrowsDown, StackFrameSizeAlignment, 0), target(TM) {}
-
+
// This method adjusts a stack offset to meet alignment rules of target.
// The fixed OFFSET (0x7ff) must be subtracted and the result aligned.
virtual int adjustAlignment(int unalignedOffset, bool growUp,
@@ -36,7 +36,7 @@
// These methods compute offsets using the frame contents for a
// particular function. The frame contents are obtained from the
// MachineCodeInfoForMethod object for the given function.
- //
+ //
int getFirstAutomaticVarOffset(MachineFunction& mcInfo, bool& growUp) const {
growUp = false;
return StaticAreaOffsetFromFP;
@@ -45,7 +45,7 @@
int getTmpAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
int getDynamicAreaOffset(MachineFunction& mcInfo, bool& growUp) const;
- virtual int getIncomingArgOffset(MachineFunction& mcInfo,
+ virtual int getIncomingArgOffset(MachineFunction& mcInfo,
unsigned argNum) const {
unsigned relativeOffset = argNum * SizeOfEachArgOnStack;
int firstArg = FirstIncomingArgOffsetFromFP;
@@ -56,7 +56,7 @@
unsigned argNum) const {
return FirstOutgoingArgOffsetFromSP + argNum * SizeOfEachArgOnStack;
}
-
+
/*----------------------------------------------------------------------
This diagram shows the stack frame layout used by llc on SparcV9 V9.
Note that only the location of automatic variables, spill area,
@@ -72,7 +72,7 @@
during a call to another function, so it is never needed when
the current function is active. This is why space can be allocated
dynamically by incrementing %sp any time within the function.
-
+
STACK FRAME LAYOUT:
...
Index: llvm/lib/Target/SparcV9/SparcV9InstrForest.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.2 llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.3
--- llvm/lib/Target/SparcV9/SparcV9InstrForest.h:1.2 Sat Oct 16 11:37:42 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrForest.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9InstrForest.h - SparcV9 BURG Instruction Selector Trees -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// A forest of BURG instruction trees (class InstrForest) which represents
@@ -62,7 +62,7 @@
/// Declarations of data and functions created by BURG
///
-namespace llvm {
+namespace llvm {
class InstrTreeNode;
};
extern short* burm_nts[];
@@ -100,7 +100,7 @@
protected:
InstrTreeNodeType treeNodeType;
Value* val;
-
+
public:
InstrTreeNode(InstrTreeNodeType nodeType, Value* _val)
: treeNodeType(nodeType), val(_val) {
@@ -116,10 +116,10 @@
inline OpLabel getOpLabel () const { return opLabel; }
inline InstrTreeNode *leftChild () const { return LeftChild; }
inline InstrTreeNode *parent () const { return Parent; }
-
+
// If right child is a list node, recursively get its *left* child
inline InstrTreeNode* rightChild() const {
- return (!RightChild ? 0 :
+ return (!RightChild ? 0 :
(RightChild->getOpLabel() == VRegListOp
? RightChild->LeftChild : RightChild));
}
Index: llvm/lib/Target/SparcV9/SparcV9InstrInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.10 llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.11
--- llvm/lib/Target/SparcV9/SparcV9InstrInfo.h:1.10 Wed Aug 18 12:44:16 2004
+++ llvm/lib/Target/SparcV9/SparcV9InstrInfo.h Thu Apr 21 18:25:42 2005
@@ -1,17 +1,17 @@
//===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This class contains information about individual instructions.
// Also see the SparcV9MachineInstrDesc array, which can be found in
// SparcV9TargetMachine.cpp.
// Other information is computed on demand, and most such functions
-// default to member functions in base class TargetInstrInfo.
+// default to member functions in base class TargetInstrInfo.
//
//===----------------------------------------------------------------------===//
@@ -41,7 +41,7 @@
// All immediate constants are in position 1 except the
// store instructions and SETxx.
- //
+ //
virtual int getImmedConstantPos(MachineOpCode opCode) const {
bool ignore;
if (this->maxImmedConstant(opCode, ignore) != 0) {
Index: llvm/lib/Target/SparcV9/SparcV9Internals.h
diff -u llvm/lib/Target/SparcV9/SparcV9Internals.h:1.119 llvm/lib/Target/SparcV9/SparcV9Internals.h:1.120
--- llvm/lib/Target/SparcV9/SparcV9Internals.h:1.119 Thu Dec 16 13:32:38 2004
+++ llvm/lib/Target/SparcV9/SparcV9Internals.h Thu Apr 21 18:25:42 2005
@@ -1,12 +1,12 @@
//===-- SparcV9Internals.h --------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file defines stuff that is to be private to the SparcV9 backend, but is
// shared among different portions of the backend.
//
@@ -41,19 +41,19 @@
SPARC_LD, /* Load instructions */
SPARC_ST, /* Store instructions */
SPARC_SINGLE, /* Instructions that must issue by themselves */
-
+
SPARC_INV, /* This should stay at the end for the next value */
SPARC_NUM_SCHED_CLASSES = SPARC_INV
};
//---------------------------------------------------------------------------
-// enum SparcV9MachineOpCode.
+// enum SparcV9MachineOpCode.
// const TargetInstrDescriptor SparcV9MachineInstrDesc[]
-//
+//
// Purpose:
// Description of UltraSparcV9 machine instructions.
-//
+//
//---------------------------------------------------------------------------
namespace V9 {
@@ -75,7 +75,7 @@
//---------------------------------------------------------------------------
// class SparcV9SchedInfo
-//
+//
// Purpose:
// Interface to instruction scheduling information for UltraSPARC.
// The parameter values above are based on UltraSPARC IIi.
@@ -107,7 +107,7 @@
// This function decomposes a single instance of such a reference.
// Return value: true if the instruction was replaced; false otherwise.
-//
+//
bool DecomposeArrayRef(GetElementPtrInst* GEP);
/// Peephole optimization pass operating on machine code
Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.7 llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.8
--- llvm/lib/Target/SparcV9/SparcV9JITInfo.h:1.7 Mon Nov 22 14:24:42 2004
+++ llvm/lib/Target/SparcV9/SparcV9JITInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9JITInfo.h - SparcV9 Target JIT interface ----------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV9 implementation of the TargetJITInfo class,
@@ -31,7 +31,7 @@
/// is not supported for this target.
///
virtual void addPassesToJITCompile(FunctionPassManager &PM);
-
+
/// replaceMachineCodeForFunction - Make it so that calling the function
/// whose machine code is at OLD turns into a call to NEW, perhaps by
/// overwriting OLD with a branch to NEW. This is used for self-modifying
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.28 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.29
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h:1.28 Wed Jun 2 21:45:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9RegClassInfo.h - Register class def'ns for SparcV9 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the register classes used by the SparcV9 target. It
@@ -26,14 +26,14 @@
//-----------------------------------------------------------------------------
struct SparcV9IntRegClass : public TargetRegClassInfo {
- SparcV9IntRegClass(unsigned ID)
+ SparcV9IntRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
inline bool isRegVolatile(int Reg) const {
- return (Reg < (int)StartOfNonVolatileRegs);
+ return (Reg < (int)StartOfNonVolatileRegs);
}
inline bool modifiedByCall(int Reg) const {
@@ -43,27 +43,27 @@
enum { // colors possible for a LR (in preferred order)
// --- following colors are volatile across function calls
// %g0 can't be used for coloring - always 0
- o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
+ o0, o1, o2, o3, o4, o5, o7, // %o0-%o5,
- // %o6 is sp,
+ // %o6 is sp,
// all %0's can get modified by a call
// --- following colors are NON-volatile across function calls
l0, l1, l2, l3, l4, l5, l6, l7, // %l0-%l7
- i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
-
+ i0, i1, i2, i3, i4, i5, // %i0-%i5: i's need not be preserved
+
// %i6 is the fp - so not allocated
// %i7 is the ret address by convention - can be used for others
// max # of colors reg coloring can allocate (NumOfAvailRegs)
// --- following colors are not available for allocation within this phase
- // --- but can appear for pre-colored ranges
+ // --- but can appear for pre-colored ranges
i6, i7, g0, g1, g2, g3, g4, g5, g6, g7, o6,
NumOfAllRegs, // Must be first AFTER registers...
-
+
//*** NOTE: If we decide to use some %g regs, they are volatile
// (see sparc64ABI)
// Move the %g regs from the end of the enumeration to just above the
@@ -76,7 +76,7 @@
StartOfNonVolatileRegs = l0,
StartOfAllRegs = o0,
-
+
ModifiedByCall = o7,
};
@@ -93,24 +93,24 @@
unsigned End,
const std::vector<bool> &IsColorUsedArr) const;
public:
- SparcV9FloatRegClass(unsigned ID)
+ SparcV9FloatRegClass(unsigned ID)
: TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {}
// This method marks the registers used for a given register number.
// This marks a single register for Float regs, but the R,R+1 pair
// for double-precision registers.
- //
+ //
virtual void markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
std::vector<bool> &IsColorUsedArr) const;
-
+
// This method finds unused registers of the specified register type,
// using the given "used" flag array IsColorUsedArr. It checks a single
// entry in the array directly for float regs, and checks the pair [R,R+1]
// for double-precision registers
// It returns -1 if no unused color is found.
- //
+ //
virtual int findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const;
@@ -121,7 +121,7 @@
inline bool isRegVolatile(int Reg) const { return true; }
enum {
- f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
+ f0, f1, f2, f3, f4, f5, f6, f7, f8, f9,
f10, f11, f12, f13, f14, f15, f16, f17, f18, f19,
f20, f21, f22, f23, f24, f25, f26, f27, f28, f29,
f30, f31, f32, f33, f34, f35, f36, f37, f38, f39,
@@ -146,16 +146,16 @@
//-----------------------------------------------------------------------------
// Int CC Register Class
// Only one integer cc register is available. However, this register is
-// referred to as %xcc or %icc when instructions like subcc are executed but
+// referred to as %xcc or %icc when instructions like subcc are executed but
// referred to as %ccr (i.e., %xcc . %icc") when this register is moved
// into an integer register using RD or WR instrcutions. So, three ids are
// allocated for the three names.
//-----------------------------------------------------------------------------
struct SparcV9IntCCRegClass : public TargetRegClassInfo {
- SparcV9IntCCRegClass(unsigned ID)
+ SparcV9IntCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 1, 3) { }
-
+
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
@@ -177,12 +177,12 @@
//-----------------------------------------------------------------------------
struct SparcV9FloatCCRegClass : public TargetRegClassInfo {
- SparcV9FloatCCRegClass(unsigned ID)
+ SparcV9FloatCCRegClass(unsigned ID)
: TargetRegClassInfo(ID, 4, 4) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const;
-
+
// according to the 64-bit SparcV9 ABI, all floating-point CC regs are
// volatile.
inline bool isRegVolatile(int Reg) const { return true; }
@@ -190,7 +190,7 @@
enum {
fcc0, fcc1, fcc2, fcc3
};
-
+
const char * const getRegName(unsigned reg) const;
};
@@ -201,14 +201,14 @@
//-----------------------------------------------------------------------------
struct SparcV9SpecialRegClass : public TargetRegClassInfo {
- SparcV9SpecialRegClass(unsigned ID)
+ SparcV9SpecialRegClass(unsigned ID)
: TargetRegClassInfo(ID, 0, 1) { }
void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const {
assert(0 && "SparcV9SpecialRegClass should never be used for allocation");
}
-
+
// all currently included special regs are volatile
inline bool isRegVolatile(int Reg) const { return true; }
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.16 llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.17
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.h:1.16 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9RegInfo.h - SparcV9 Target Register Info ---------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file is used to describe the register file of the SparcV9 target to
@@ -43,7 +43,7 @@
const unsigned RegClassID; // integer ID of a reg class
const unsigned NumOfAvailRegs; // # of avail for coloring -without SP etc.
const unsigned NumOfAllRegs; // # of all registers -including SP,g0 etc.
-
+
public:
inline unsigned getRegClassID() const { return RegClassID; }
inline unsigned getNumOfAvailRegs() const { return NumOfAvailRegs; }
@@ -52,7 +52,7 @@
// This method marks the registers used for a given register number.
// This defaults to marking a single register but may mark multiple
// registers when a single number denotes paired registers.
- //
+ //
virtual void markColorsUsed(unsigned RegInClass,
int UserRegType,
int RegTypeWanted,
@@ -68,7 +68,7 @@
// checking a single entry in the array directly, but that can be overridden
// for paired registers and other such silliness.
// It returns -1 if no unused color is found.
- //
+ //
virtual int findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const {
// find first unused color in the IsColorUsedArr directly
@@ -81,7 +81,7 @@
}
// This method should find a color which is not used by neighbors
- // (i.e., a false position in IsColorUsedArr) and
+ // (i.e., a false position in IsColorUsedArr) and
virtual void colorIGNode(IGNode *Node,
const std::vector<bool> &IsColorUsedArr) const = 0;
@@ -107,8 +107,8 @@
protected:
// A vector of all machine register classes
//
- std::vector<const TargetRegClassInfo *> MachineRegClassArr;
-
+ std::vector<const TargetRegClassInfo *> MachineRegClassArr;
+
public:
const TargetMachine ⌖
@@ -119,7 +119,7 @@
// According the definition of a MachineOperand class, a Value in a
- // machine instruction can go into either a normal register or a
+ // machine instruction can go into either a normal register or a
// condition code register. If isCCReg is true below, the ID of the condition
// code register class will be returned. Otherwise, the normal register
// class (eg. int, float) must be returned.
@@ -139,12 +139,12 @@
return classId;
}
- unsigned int getNumOfRegClasses() const {
- return MachineRegClassArr.size();
- }
+ unsigned int getNumOfRegClasses() const {
+ return MachineRegClassArr.size();
+ }
- const TargetRegClassInfo *getMachineRegClass(unsigned i) const {
- return MachineRegClassArr[i];
+ const TargetRegClassInfo *getMachineRegClass(unsigned i) const {
+ return MachineRegClassArr[i];
}
// getZeroRegNum - returns the register that is hardwired to always contain
@@ -156,13 +156,13 @@
// method args and return values etc.) with specific hardware registers
// as required. See SparcRegInfo.cpp for the implementation for Sparc.
//
- void suggestRegs4MethodArgs(const Function *Func,
+ void suggestRegs4MethodArgs(const Function *Func,
LiveRangeInfo& LRI) const;
- void suggestRegs4CallArgs(MachineInstr *CallI,
+ void suggestRegs4CallArgs(MachineInstr *CallI,
LiveRangeInfo& LRI) const;
- void suggestReg4RetValue(MachineInstr *RetI,
+ void suggestReg4RetValue(MachineInstr *RetI,
LiveRangeInfo& LRI) const;
void colorMethodArgs(const Function *Func,
@@ -182,7 +182,7 @@
inline bool modifiedByCall(int RegClassID, int Reg) const {
return MachineRegClassArr[RegClassID]->modifiedByCall(Reg);
}
-
+
// getCallAddressReg - Returns the reg used for pushing the address
// when a method is called. This can be used for other purposes
// between calls
@@ -207,8 +207,8 @@
// and returns the class ID in regClassID.
int getClassRegNum(int uRegNum, unsigned& regClassID) const {
if (uRegNum == getInvalidRegNum()) { return getInvalidRegNum(); }
-
- int totalRegs = 0, rcid = 0, NC = getNumOfRegClasses();
+
+ int totalRegs = 0, rcid = 0, NC = getNumOfRegClasses();
while (rcid < NC &&
uRegNum>= totalRegs+(int)MachineRegClassArr[rcid]->getNumOfAllRegs())
{
@@ -222,20 +222,20 @@
regClassID = rcid;
return uRegNum - totalRegs;
}
-
+
// Returns the assembly-language name of the specified machine register.
- //
+ //
const char * const getUnifiedRegName(int UnifiedRegNum) const {
unsigned regClassID = getNumOfRegClasses(); // initialize to invalid value
int regNumInClass = getClassRegNum(UnifiedRegNum, regClassID);
return MachineRegClassArr[regClassID]->getRegName(regNumInClass);
}
- // This method gives the the number of bytes of stack space allocated
+ // This method gives the the number of bytes of stack space allocated
// to a register when it is spilled to the stack, according to its
// register type.
//
- // For SparcV9, currently we allocate 8 bytes on stack for all
+ // For SparcV9, currently we allocate 8 bytes on stack for all
// register types. We can optimize this later if necessary to save stack
// space (However, should make sure that stack alignment is correct)
//
@@ -256,11 +256,11 @@
// function args and return values etc.) with specific hardware registers
// as required. See SparcV9RegInfo.cpp for the implementation.
//
- void suggestReg4RetAddr(MachineInstr *RetMI,
+ void suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo &LRI) const;
void suggestReg4CallAddr(MachineInstr *CallMI, LiveRangeInfo &LRI) const;
-
+
// Helper used by the all the getRegType() functions.
int getRegTypeForClassAndType(unsigned regClassID, const Type* type) const;
@@ -280,11 +280,11 @@
// The actual register classes in the SparcV9
//
- // **** WARNING: If this enum order is changed, also modify
- // getRegisterClassOfValue method below since it assumes this particular
+ // **** WARNING: If this enum order is changed, also modify
+ // getRegisterClassOfValue method below since it assumes this particular
// order for efficiency.
- //
- enum RegClassIDs {
+ //
+ enum RegClassIDs {
IntRegClassID, // Integer
FloatRegClassID, // Float (both single/double)
IntCCRegClassID, // Int Condition Code
@@ -300,7 +300,7 @@
}
// Returns the register containing the return address.
- // It should be made sure that this register contains the return
+ // It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned getReturnAddressReg() const;
@@ -310,15 +310,15 @@
//
unsigned const getNumOfIntArgRegs() const { return NumOfIntArgRegs; }
unsigned const getNumOfFloatArgRegs() const { return NumOfFloatArgRegs; }
-
+
// Compute which register can be used for an argument, if any
- //
+ //
int regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const;
int regNumForFPArg(unsigned RegType, bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const;
-
+
// method used for printing a register for debugging purposes
//
@@ -331,7 +331,7 @@
const Value * getCallInstIndirectAddrVal(const MachineInstr *CallMI) const;
// The following methods are used to generate "copy" machine instructions
- // for an architecture. Currently they are used in TargetRegClass
+ // for an architecture. Currently they are used in TargetRegClass
// interface. However, they can be moved to TargetInstrInfo interface if
// necessary.
//
Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.6 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.7
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h:1.6 Sun Aug 15 17:15:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9RegisterInfo.h - SparcV9 Register Information Impl -*- C++ -*-==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains the SparcV9 implementation of the MRegisterInfo class.
@@ -66,7 +66,7 @@
/* 5 */ o5, o7, l0, l1, l2,
/* 10 */ l3, l4, l5, l6, l7,
/* 15 */ i0, i1, i2, i3, i4,
- /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
+ /* 20 */ i5, i6, i7, g0, g1, // i6 is frame ptr, i7 is ret addr, g0 is zero
/* 25 */ g2, g3, g4, g5, g6,
/* 30 */ g7, o6, // o6 is stack ptr
@@ -88,7 +88,7 @@
/* 90 */ f58, f59, f60, f61, f62,
/* 95 */ f63,
- // SparcV9IntCCRegClass(IntCCRegClassID)
+ // SparcV9IntCCRegClass(IntCCRegClassID)
// - unified register numbers 96 ... 98 (3 regs)
/* 96 */ xcc, icc, ccr,
Index: llvm/lib/Target/SparcV9/SparcV9Relocations.h
diff -u llvm/lib/Target/SparcV9/SparcV9Relocations.h:1.1 llvm/lib/Target/SparcV9/SparcV9Relocations.h:1.2
--- llvm/lib/Target/SparcV9/SparcV9Relocations.h:1.1 Sun Nov 21 18:40:51 2004
+++ llvm/lib/Target/SparcV9/SparcV9Relocations.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9Relocations.h - SparcV9 Code Relocations ----------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the SparcV9 target-specific relocation types.
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.h
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.11 llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.12
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.h:1.11 Sat Jul 10 21:45:11 2004
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.h Thu Apr 21 18:25:42 2005
@@ -1,12 +1,12 @@
//===-- SparcV9TargetMachine.h - Define TargetMachine for SparcV9 -*- C++ -*-=//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file declares the top-level SparcV9 target machine.
//
//===----------------------------------------------------------------------===//
@@ -33,7 +33,7 @@
SparcV9JITInfo jitInfo;
public:
SparcV9TargetMachine(const Module &M, IntrinsicLowering *IL);
-
+
virtual const TargetInstrInfo *getInstrInfo() const { return &instrInfo; }
virtual const TargetSchedInfo *getSchedInfo() const { return &schedInfo; }
virtual const SparcV9RegInfo *getRegInfo() const { return ®Info; }
Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.h
diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.3 llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.4
--- llvm/lib/Target/SparcV9/SparcV9TmpInstr.h:1.3 Fri Jan 28 18:36:59 2005
+++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.h Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9TmpInstr.h ---------------------------------------*- C++ -*-===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Definition of class for temporary intermediate values used within the current
@@ -22,7 +22,7 @@
/// TmpInstruction - This class represents temporary intermediate
/// values used within the SparcV9 machine code for an LLVM instruction.
-///
+///
class TmpInstruction : public Instruction {
Use Ops[2];
TmpInstruction(const TmpInstruction &TI);
@@ -31,7 +31,7 @@
// s1 must be a valid value. s2 may be NULL.
TmpInstruction(MachineCodeForInstruction &mcfi,
Value *s1, Value *s2 = 0, const std::string &name = "");
-
+
// Constructor that uses the type of S1 as the type of the temporary,
// but does not require a MachineCodeForInstruction.
// s1 must be a valid value. s2 may be NULL.
@@ -42,13 +42,13 @@
TmpInstruction(MachineCodeForInstruction& mcfi,
const Type *Ty, Value *s1 = 0, Value* s2 = 0,
const std::string &name = "");
-
+
virtual Instruction *clone() const {
assert(0 && "Cannot clone TmpInstructions!");
return 0;
}
virtual const char *getOpcodeName() const { return "TmpInstruction"; }
-
+
// Methods for support type inquiry through isa, cast, and dyn_cast:
static inline bool classof(const TmpInstruction *) { return true; }
static inline bool classof(const Instruction *I) {
Index: llvm/lib/Target/SparcV9/DecomposeMultiDimRefs.cpp
diff -u llvm/lib/Target/SparcV9/DecomposeMultiDimRefs.cpp:1.2 llvm/lib/Target/SparcV9/DecomposeMultiDimRefs.cpp:1.3
--- llvm/lib/Target/SparcV9/DecomposeMultiDimRefs.cpp:1.2 Sat Nov 6 18:43:24 2004
+++ llvm/lib/Target/SparcV9/DecomposeMultiDimRefs.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- llvm/Transforms/DecomposeMultiDimRefs.cpp - Lower array refs to 1D -===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// DecomposeMultiDimRefs - Convert multi-dimensional references consisting of
@@ -57,28 +57,28 @@
}
// Function: DecomposeArrayRef()
-//
+//
// For any GetElementPtrInst with 2 or more array and structure indices:
-//
+//
// opCode CompositeType* P, [uint|ubyte] idx1, ..., [uint|ubyte] idxN
-//
+//
// this function generates the following sequence:
-//
+//
// ptr1 = getElementPtr P, idx1
// ptr2 = getElementPtr ptr1, 0, idx2
// ...
// ptrN-1 = getElementPtr ptrN-2, 0, idxN-1
// opCode ptrN-1, 0, idxN // New-MAI
-//
+//
// Then it replaces the original instruction with this sequence,
// and replaces all uses of the original instruction with New-MAI.
// If idx1 is 0, we simply omit the first getElementPtr instruction.
-//
+//
// On return: BBI points to the instruction after the current one
// (whether or not *BBI was replaced).
-//
+//
// Return value: true if the instruction was replaced; false otherwise.
-//
+//
bool llvm::DecomposeArrayRef(GetElementPtrInst* GEP) {
if (GEP->getNumIndices() < 2
|| (GEP->getNumIndices() == 2
@@ -97,7 +97,7 @@
User::const_op_iterator OI = GEP->idx_begin(), OE = GEP->idx_end();
for (; OI+1 != OE; ++OI) {
std::vector<Value*> Indices;
-
+
// If this is the first index and is 0, skip it and move on!
if (OI == GEP->idx_begin()) {
if (isZeroConst (*OI))
Index: llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp
diff -u llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.15 llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.16
--- llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp:1.15 Sun Sep 19 23:46:39 2004
+++ llvm/lib/Target/SparcV9/EmitBytecodeToAssembly.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- EmitBytecodeToAssembly.cpp - Emit bytecode to SparcV9 .s File ------==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the pass that writes LLVM bytecode as data to a sparc
@@ -31,7 +31,7 @@
typedef int int_type;
typedef std::streampos pos_type;
typedef std::streamoff off_type;
-
+
sparcasmbuf(std::ostream &On) : BaseStr(On) {}
virtual int_type overflow(int_type C) {
@@ -65,19 +65,19 @@
const std::string &symName) {
// Prologue:
// Output a comment describing the object.
- Out << "!" << comment << "\n";
+ Out << "!" << comment << "\n";
// Switch the current section to .rodata in the assembly output:
- Out << "\t.section \".rodata\"\n\t.align 8\n";
+ Out << "\t.section \".rodata\"\n\t.align 8\n";
// Output a global symbol naming the object:
- Out << "\t.global " << symName << "\n";
- Out << "\t.type " << symName << ",#object\n";
- Out << symName << ":\n";
+ Out << "\t.global " << symName << "\n";
+ Out << "\t.type " << symName << ",#object\n";
+ Out << symName << ":\n";
}
static void writeEpilogue (std::ostream &Out, const std::string &symName) {
// Epilogue:
// Output a local symbol marking the end of the object:
- Out << ".end_" << symName << ":\n";
+ Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
<< "\n";
@@ -90,7 +90,7 @@
SparcV9BytecodeWriter(std::ostream &out) : Out(out) {}
const char *getPassName() const { return "Emit Bytecode to SparcV9 Assembly";}
-
+
virtual bool runOnModule(Module &M) {
// Write an object containing the bytecode to the SPARC assembly stream
writePrologue (Out, "LLVM BYTECODE OUTPUT", "LLVMBytecode");
@@ -101,7 +101,7 @@
// Write an object containing its length as an integer to the
// SPARC assembly stream
writePrologue (Out, "LLVM BYTECODE LENGTH", "llvm_length");
- Out <<"\t.word\t.end_LLVMBytecode-LLVMBytecode\n";
+ Out <<"\t.word\t.end_LLVMBytecode-LLVMBytecode\n";
writeEpilogue (Out, "llvm_length");
return false;
Index: llvm/lib/Target/SparcV9/InternalGlobalMapper.cpp
diff -u llvm/lib/Target/SparcV9/InternalGlobalMapper.cpp:1.6 llvm/lib/Target/SparcV9/InternalGlobalMapper.cpp:1.7
--- llvm/lib/Target/SparcV9/InternalGlobalMapper.cpp:1.6 Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV9/InternalGlobalMapper.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- InternalGlobalMapper.cpp - Mapping Info for Internal Globals ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// InternalGlobalMapper is a pass that helps the runtime trace optimizer map
@@ -71,7 +71,7 @@
std::vector<Constant *> FieldValues;
FieldValues.push_back (ConstantUInt::get (Type::UIntTy, gvvector.size ()));
FieldValues.push_back (ConstantArray::get (ATy, gvvector));
-
+
// Add the constant struct to M as an external global symbol named
// "_llvm_internalGlobals".
new GlobalVariable (STy, true, GlobalValue::ExternalLinkage,
Index: llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp
diff -u llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.3 llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.4
--- llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp:1.3 Tue Aug 24 01:41:38 2004
+++ llvm/lib/Target/SparcV9/MachineCodeForInstruction.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- MachineCodeForInstruction.cpp -------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Container for the sequence of MachineInstrs created for a single
@@ -13,7 +13,7 @@
// they can be deleted when they are no longer needed, and finally, it also
// holds some extra information for 'call' Instructions (using the
// CallArgsDescriptor object, which is also implemented in this file).
-//
+//
//===----------------------------------------------------------------------===//
#include "MachineCodeForInstruction.h"
@@ -46,11 +46,11 @@
MachineCodeForInstruction::~MachineCodeForInstruction() {
// Let go of all uses in temp. instructions
dropAllReferences();
-
+
// Free the Value objects created to hold intermediate values
for (unsigned i=0, N=tempVec.size(); i < N; i++)
delete tempVec[i];
-
+
// do not free the MachineInstr objects allocated. they are managed
// by the ilist in MachineBasicBlock
@@ -76,7 +76,7 @@
// Enter this object in the MachineCodeForInstr object of the CallInst.
// This transfers ownership of this object.
- MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this);
+ MachineCodeForInstruction::get(callInstr).setCallArgsDescriptor(this);
}
CallInst *CallArgsDescriptor::getReturnValue() const {
@@ -90,7 +90,7 @@
/// the CallArgsDescriptor from the MachineCodeForInstruction object for the
/// CallInstr. This is roundabout but avoids adding a new map or annotation
/// just to keep track of CallArgsDescriptors.
-///
+///
CallArgsDescriptor *CallArgsDescriptor::get(const MachineInstr *MI) {
const Value *retAddrVal = 0;
if ((MI->getOperand (0).getType () == MachineOperand::MO_MachineRegister
@@ -110,7 +110,7 @@
const CallInst* callInstr = cast<CallInst>(retAddrReg->getOperand(0));
CallArgsDescriptor* desc =
- MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor();
+ MachineCodeForInstruction::get(callInstr).getCallArgsDescriptor();
assert(desc->getCallInst()==callInstr && "Incorrect call args descriptor?");
return desc;
}
Index: llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp
diff -u llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.2 llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.3
--- llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp:1.2 Wed Aug 18 13:13:34 2004
+++ llvm/lib/Target/SparcV9/MachineFunctionInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,12 +1,12 @@
//===-- SparcV9FunctionInfo.cpp -------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This implements the SparcV9 specific MachineFunctionInfo class.
//
//===----------------------------------------------------------------------===//
@@ -25,7 +25,7 @@
unsigned &maxOptionalNumArgs)
{
unsigned maxSize = 0;
-
+
for (Function::const_iterator BB = F->begin(), BBE = F->end(); BB !=BBE; ++BB)
for (BasicBlock::const_iterator I = BB->begin(), E = BB->end(); I != E; ++I)
if (const CallInst *callInst = dyn_cast<CallInst>(I))
@@ -34,16 +34,16 @@
int numExtra = numOperands-6;
if (numExtra <= 0)
continue;
-
+
unsigned sizeForThisCall = numExtra * 8;
-
+
if (maxSize < sizeForThisCall)
maxSize = sizeForThisCall;
-
+
if ((int)maxOptionalNumArgs < numExtra)
maxOptionalNumArgs = (unsigned) numExtra;
}
-
+
return maxSize;
}
@@ -55,7 +55,7 @@
// This function is similar to the corresponding function in EmitAssembly.cpp
// but they are unrelated. This one does not align at more than a
// double-word boundary whereas that one might.
-//
+//
inline unsigned
SizeToAlignment(unsigned size, const TargetMachine& target)
{
@@ -108,9 +108,9 @@
assert(! automaticVarsAreaFrozen &&
"Size of auto vars area has been used to compute an offset so "
"no more automatic vars should be allocated!");
-
+
// Check if we've allocated a stack slot for this value already
- //
+ //
hash_map<const Value*, int>::const_iterator pair = offsets.find(val);
if (pair != offsets.end())
return pair->second;
@@ -128,19 +128,19 @@
assert(! spillsAreaFrozen &&
"Size of reg spills area has been used to compute an offset so "
"no more register spill slots should be allocated!");
-
+
unsigned size = MF.getTarget().getTargetData().getTypeSize(type);
unsigned char align = MF.getTarget().getTargetData().getTypeAlignment(type);
-
+
bool growUp;
int firstOffset = MF.getTarget().getFrameInfo()->getRegSpillAreaOffset(MF, growUp);
-
+
int offset = growUp? firstOffset + getRegSpillsSize()
: firstOffset - (getRegSpillsSize() + size);
int aligned = MF.getTarget().getFrameInfo()->adjustAlignment(offset, growUp, align);
size += abs(aligned - offset); // include alignment padding in size
-
+
incrementRegSpillsSize(size); // update size of reg. spills area
return aligned;
Index: llvm/lib/Target/SparcV9/MappingInfo.cpp
diff -u llvm/lib/Target/SparcV9/MappingInfo.cpp:1.21 llvm/lib/Target/SparcV9/MappingInfo.cpp:1.22
--- llvm/lib/Target/SparcV9/MappingInfo.cpp:1.21 Tue Oct 19 00:15:21 2004
+++ llvm/lib/Target/SparcV9/MappingInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- MappingInfo.cpp - create LLVM info and output to .s file -----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains a FunctionPass called MappingInfoAsmPrinter,
@@ -36,7 +36,7 @@
namespace llvm {
namespace {
- class MappingInfoAsmPrinter : public FunctionPass {
+ class MappingInfoAsmPrinter : public FunctionPass {
std::ostream &Out;
public:
MappingInfoAsmPrinter(std::ostream &out) : Out(out){}
@@ -78,8 +78,8 @@
// Now, write out the maps.
BBMIMap.dumpAssembly (Out);
- return false;
-}
+ return false;
+}
/// writeNumber - Write out the number X as a sequence of .byte
/// directives to the current output stream Out. This method performs a
@@ -146,7 +146,7 @@
create_BB_to_MInumber_Key(FI, BBkey);
selectOutputMap (Map);
- MachineFunction &MF = MachineFunction::get(&FI);
+ MachineFunction &MF = MachineFunction::get(&FI);
for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
BI != BE; ++BI, ++bb) {
MachineBasicBlock &miBB = *BI;
@@ -165,19 +165,19 @@
const std::string &symName) {
// Prologue:
// Output a comment describing the object.
- Out << "!" << comment << "\n";
+ Out << "!" << comment << "\n";
// Switch the current section to .rodata in the assembly output:
- Out << "\t.section \".rodata\"\n\t.align 8\n";
+ Out << "\t.section \".rodata\"\n\t.align 8\n";
// Output a global symbol naming the object:
- Out << "\t.global " << symName << "\n";
- Out << "\t.type " << symName << ",#object\n";
- Out << symName << ":\n";
+ Out << "\t.global " << symName << "\n";
+ Out << "\t.type " << symName << ",#object\n";
+ Out << symName << ":\n";
}
static void writeEpilogue (std::ostream &Out, const std::string &symName) {
// Epilogue:
// Output a local symbol marking the end of the object:
- Out << ".end_" << symName << ":\n";
+ Out << ".end_" << symName << ":\n";
// Output size directive giving the size of the object:
Out << "\t.size " << symName << ", .end_" << symName << "-" << symName
<< "\n";
@@ -199,7 +199,7 @@
///
bool MappingInfoAsmPrinter::doFinalization (Module &M) {
unsigned f;
-
+
writePrologue(Out, "FUNCTION TO BB MAP", "FunctionBB");
f=0;
for(Module::iterator FI = M.begin (), FE = M.end (); FE != FI; ++FI) {
@@ -209,7 +209,7 @@
++f;
}
writeEpilogue(Out, "FunctionBB");
-
+
return false;
}
Index: llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.126 llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.127
--- llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp:1.126 Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV9/SparcV9AsmPrinter.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9AsmPrinter.cpp - Emit SparcV9 Specific .s File --------------==//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements all of the stuff necessary to output a .s file from
@@ -110,7 +110,7 @@
/// Get the size of the constant for the given target.
/// If this is an unsized array, return 0.
- ///
+ ///
inline unsigned int
ConstantToSize(const Constant* CV, const TargetMachine& target) {
if (const ConstantArray* CVA = dyn_cast<ConstantArray>(CV)) {
@@ -118,13 +118,13 @@
if (ArrayTypeIsString(aty))
return 1 + CVA->getNumOperands();
}
-
+
return findOptimalStorageSize(target, CV->getType());
}
/// Align data larger than one L1 cache line on L1 cache line boundaries.
/// Align all smaller data on the next higher 2^x boundary (4, 8, ...).
- ///
+ ///
inline unsigned int
SizeToAlignment(unsigned int size, const TargetMachine& target) {
const unsigned short cacheLineSize = 16;
@@ -137,7 +137,7 @@
}
/// Get the size of the type and then use SizeToAlignment.
- ///
+ ///
inline unsigned int
TypeToAlignment(const Type* type, const TargetMachine& target) {
return SizeToAlignment(findOptimalStorageSize(target, type), target);
@@ -150,7 +150,7 @@
if (const ConstantArray* CVA = dyn_cast<ConstantArray>(CV))
if (ArrayTypeIsString(cast<ArrayType>(CVA->getType())))
return SizeToAlignment(1 + CVA->getNumOperands(), target);
-
+
return TypeToAlignment(CV->getType(), target);
}
@@ -177,7 +177,7 @@
AsmPrinter(std::ostream &os, const TargetMachine &T)
: /* idTable(0), */ O(os), TM(T), CurSection(Unknown) {}
-
+
~AsmPrinter() {
delete Mang;
}
@@ -212,9 +212,9 @@
void printConstant(const Constant* CV, std::string valID = "") {
if (valID.length() == 0)
valID = getID(CV);
-
+
O << "\t.align\t" << ConstantToAlignment(CV, TM) << "\n";
-
+
// Print .size and .type only if it is not a string.
if (const ConstantArray *CVA = dyn_cast<ConstantArray>(CV))
if (CVA->isString()) {
@@ -223,15 +223,15 @@
O << "\t" << ".ascii" << "\t" << getAsCString(CVA) << "\n";
return;
}
-
+
O << "\t.type" << "\t" << valID << ",#object\n";
unsigned int constSize = ConstantToSize(CV, TM);
if (constSize)
O << "\t.size" << "\t" << valID << "," << constSize << "\n";
-
+
O << valID << ":\n";
-
+
printConstantValueOnly(CV);
}
@@ -279,7 +279,7 @@
return "";
}
- // Combines expressions
+ // Combines expressions
inline std::string ConstantArithExprToString(const ConstantExpr* CE,
const TargetMachine &TM,
const std::string &op) {
@@ -295,7 +295,7 @@
/// valToExprString - Helper function for ConstantExprToString().
/// Appends result to argument string S.
- ///
+ ///
std::string valToExprString(const Value* V, const TargetMachine& target);
};
} // End anonymous namespace
@@ -307,18 +307,18 @@
assert(CV->getType() != Type::VoidTy &&
CV->getType() != Type::LabelTy &&
"Unexpected type for Constant");
-
+
assert((!isa<ConstantArray>(CV) && ! isa<ConstantStruct>(CV))
&& "Aggregate types should be handled outside this function");
-
+
O << "\t" << TypeToDataDirective(CV->getType()) << "\t";
-
+
if (const GlobalValue* GV = dyn_cast<GlobalValue>(CV)) {
O << getID(GV) << "\n";
} else if (isa<ConstantPointerNull>(CV) || isa<UndefValue>(CV)) {
// Null pointer value
O << "0\n";
- } else if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) {
+ } else if (const ConstantExpr* CE = dyn_cast<ConstantExpr>(CV)) {
// Constant expression built from operators, constants, and symbolic addrs
O << ConstantExprToString(CE, TM) << "\n";
} else if (CV->getType()->isPrimitiveType()) {
@@ -332,14 +332,14 @@
if (CV->getType() == Type::FloatTy) {
float FVal = (float)Val;
char *ProxyPtr = (char*)&FVal; // Abide by C TBAA rules
- O << *(unsigned int*)ProxyPtr;
+ O << *(unsigned int*)ProxyPtr;
} else if (CV->getType() == Type::DoubleTy) {
char *ProxyPtr = (char*)&Val; // Abide by C TBAA rules
- O << *(uint64_t*)ProxyPtr;
+ O << *(uint64_t*)ProxyPtr;
} else {
assert(0 && "Unknown floating point type!");
}
-
+
O << "\t! " << CV->getType()->getDescription()
<< " value: " << Val << "\n";
} else if (const ConstantBool *CB = dyn_cast<ConstantBool>(CV)) {
@@ -468,7 +468,7 @@
/// valToExprString - Helper function for ConstantExprToString().
/// Appends result to argument string S.
-///
+///
std::string AsmPrinter::valToExprString(const Value* V,
const TargetMachine& target) {
std::string S;
@@ -536,13 +536,13 @@
private :
void emitBasicBlock(const MachineBasicBlock &MBB);
void emitMachineInst(const MachineInstr *MI);
-
+
unsigned int printOperands(const MachineInstr *MI, unsigned int opNum);
void printOneOperand(const MachineOperand &Op, MachineOpCode opCode);
bool OpIsBranchTargetLabel(const MachineInstr *MI, unsigned int opNum);
bool OpIsMemoryAddressBase(const MachineInstr *MI, unsigned int opNum);
-
+
unsigned getOperandMask(unsigned Opcode) {
switch (Opcode) {
case V9::SUBccr:
@@ -608,7 +608,7 @@
MachineOpCode opCode)
{
bool needBitsFlag = true;
-
+
if (mop.isHiBits32())
O << "%lm(";
else if (mop.isLoBits32())
@@ -619,7 +619,7 @@
O << "%hm(";
else
needBitsFlag = false;
-
+
switch (mop.getType())
{
case MachineOperand::MO_VirtualRegister:
@@ -627,7 +627,7 @@
case MachineOperand::MO_MachineRegister:
{
int regNum = (int)mop.getReg();
-
+
if (regNum == TM.getRegInfo()->getInvalidRegNum()) {
// better to print code with NULL registers than to die
O << "<NULL VALUE>";
@@ -636,7 +636,7 @@
}
break;
}
-
+
case MachineOperand::MO_ConstantPoolIndex:
{
O << ".CPI_" << getID(currFunction)
@@ -648,7 +648,7 @@
{
const Value *Val = mop.getVRegValue();
assert(Val && "\tNULL Value in SparcV9AsmPrinter");
-
+
if (const BasicBlock *BB = dyn_cast<BasicBlock>(Val))
O << getID(BB);
else if (const Function *F = dyn_cast<Function>(Val))
@@ -661,7 +661,7 @@
assert(0 && "Unrecognized value in SparcV9AsmPrinter");
break;
}
-
+
case MachineOperand::MO_SignExtendedImmed:
O << mop.getImmedValue();
break;
@@ -669,12 +669,12 @@
case MachineOperand::MO_UnextendedImmed:
O << (uint64_t) mop.getImmedValue();
break;
-
+
default:
O << mop; // use dump field
break;
}
-
+
if (needBitsFlag)
O << ")";
}
@@ -688,7 +688,7 @@
O << "\t" << TM.getInstrInfo()->getName(Opcode) << "\t";
unsigned Mask = getOperandMask(Opcode);
-
+
bool NeedComma = false;
unsigned N = 1;
for (unsigned OpNum = 0; OpNum < MI->getNumOperands(); OpNum += N)
@@ -698,7 +698,7 @@
N = printOperands(MI, OpNum);
} else
N = 1;
-
+
O << "\n";
++EmittedInsts;
}
@@ -751,7 +751,7 @@
void SparcV9AsmPrinter::printGlobalVariable(const GlobalVariable* GV) {
if (GV->hasExternalLinkage())
O << "\t.global\t" << getID(GV) << "\n";
-
+
if (GV->hasInitializer() &&
!(GV->getInitializer()->isNullValue() ||
isa<UndefValue>(GV->getInitializer()))) {
Index: llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.16 llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.17
--- llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp:1.16 Sat Apr 9 01:27:14 2005
+++ llvm/lib/Target/SparcV9/SparcV9BurgISel.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9BurgISel.cpp - SparcV9 BURG-based Instruction Selector ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// SparcV9 BURG-based instruction selector. It uses the SSA graph to
@@ -56,7 +56,7 @@
class InstructionNode : public InstrTreeNode {
bool codeIsFoldedIntoParent;
-
+
public:
InstructionNode(Instruction *_instr);
@@ -73,7 +73,7 @@
static inline bool classof(const InstrTreeNode *N) {
return N->getNodeType() == InstrTreeNode::NTInstructionNode;
}
-
+
protected:
virtual void dumpNode(int indent) const;
};
@@ -106,9 +106,9 @@
class ConstantNode : public InstrTreeNode {
public:
- ConstantNode(Constant *constVal)
+ ConstantNode(Constant *constVal)
: InstrTreeNode(NTConstNode, (Value*)constVal) {
- opLabel = ConstantNodeOp;
+ opLabel = ConstantNodeOp;
}
Constant *getConstVal() const { return (Constant*) val;}
// Methods to support type inquiry through isa, cast, and dyn_cast:
@@ -142,7 +142,7 @@
/// instructions O and I if: (1) Instruction O computes an operand used
/// by instruction I, and (2) O and I are part of the same basic block,
/// and (3) O has only a single use, viz., I.
-///
+///
class InstrForest : private hash_map<const Instruction *, InstructionNode*> {
public:
// Use a vector for the root set to get a deterministic iterator
@@ -152,29 +152,29 @@
typedef std::vector<InstructionNode*> RootSet;
typedef RootSet:: iterator root_iterator;
typedef RootSet::const_iterator const_root_iterator;
-
+
private:
RootSet treeRoots;
-
+
public:
/*ctor*/ InstrForest (Function *F);
/*dtor*/ ~InstrForest ();
-
+
/// getTreeNodeForInstr - Returns the tree node for an Instruction.
///
inline InstructionNode *getTreeNodeForInstr(Instruction* instr) {
return (*this)[instr];
}
-
+
/// Iterators for the root nodes for all the trees.
///
const_root_iterator roots_begin() const { return treeRoots.begin(); }
root_iterator roots_begin() { return treeRoots.begin(); }
const_root_iterator roots_end () const { return treeRoots.end(); }
root_iterator roots_end () { return treeRoots.end(); }
-
+
void dump() const;
-
+
private:
// Methods used to build the instruction forest.
void eraseRoot (InstructionNode* node);
@@ -187,7 +187,7 @@
void InstrTreeNode::dump(int dumpChildren, int indent) const {
dumpNode(indent);
-
+
if (dumpChildren) {
if (LeftChild)
LeftChild->dump(dumpChildren, indent+1);
@@ -201,7 +201,7 @@
opLabel = I->getOpcode();
// Distinguish special cases of some instructions such as Ret and Br
- //
+ //
if (opLabel == Instruction::Ret && cast<ReturnInst>(I)->getReturnValue()) {
opLabel = RetValueOp; // ret(value) operation
}
@@ -258,7 +258,7 @@
void VRegListNode::dumpNode(int indent) const {
for (int i=0; i < indent; i++)
std::cerr << " ";
-
+
std::cerr << "List" << "\n";
}
@@ -277,7 +277,7 @@
void LabelNode::dumpNode(int indent) const {
for (int i=0; i < indent; i++)
std::cerr << " ";
-
+
std::cerr << "Label " << *getValue() << "\n";
}
@@ -336,16 +336,16 @@
assert(treeNode->getInstruction() == instr);
return treeNode;
}
-
+
// Otherwise, create a new tree node for this instruction.
treeNode = new InstructionNode(instr);
noteTreeNodeForInstr(instr, treeNode);
-
+
if (instr->getOpcode() == Instruction::Call) {
// Operands of call instruction
return treeNode;
}
-
+
// If the instruction has more than 2 instruction operands,
// then we need to create artificial list nodes to hold them.
// (Note that we only count operands that get tree nodes, and not
@@ -357,12 +357,12 @@
// if a fixed array is too small.
int numChildren = 0;
InstrTreeNode** childArray = new InstrTreeNode*[instr->getNumOperands()];
-
+
// Walk the operands of the instruction
for (Instruction::op_iterator O = instr->op_begin(); O!=instr->op_end();
++O) {
Value* operand = *O;
-
+
// Check if the operand is a data value, not an branch label, type,
// method or module. If the operand is an address type (i.e., label
// or method) that is used in an non-branching operation, e.g., `add'.
@@ -371,7 +371,7 @@
bool includeAddressOperand =
(isa<BasicBlock>(operand) || isa<Function>(operand))
&& !instr->isTerminator();
-
+
if (includeAddressOperand || isa<Instruction>(operand) ||
isa<Constant>(operand) || isa<Argument>(operand)) {
// This operand is a data value.
@@ -412,7 +412,7 @@
childArray[numChildren++] = opTreeNode;
}
}
-
+
// Add any selected operands as children in the tree.
// Certain instructions can have more than 2 in some instances (viz.,
// a CALL or a memory access -- LOAD, STORE, and GetElemPtr -- to an
@@ -420,7 +420,7 @@
// a right-leaning binary tree with the operand nodes at the leaves
// and VRegList nodes as internal nodes.
InstrTreeNode *parent = treeNode;
-
+
if (numChildren > 2) {
unsigned instrOpcode = treeNode->getInstruction()->getOpcode();
assert(instrOpcode == Instruction::PHI ||
@@ -429,13 +429,13 @@
instrOpcode == Instruction::Store ||
instrOpcode == Instruction::GetElementPtr);
}
-
+
// Insert the first child as a direct child
if (numChildren >= 1)
setLeftChild(parent, childArray[0]);
int n;
-
+
// Create a list node for children 2 .. N-1, if any
for (n = numChildren-1; n >= 2; n--) {
// We have more than two children
@@ -444,7 +444,7 @@
setLeftChild(listNode, childArray[numChildren - n]);
parent = listNode;
}
-
+
// Now insert the last remaining child (if any).
if (numChildren >= 2) {
assert(n == 1);
@@ -464,8 +464,8 @@
///
enum SelectDebugLevel_t {
Select_NoDebugInfo,
- Select_PrintMachineCode,
- Select_DebugInstTrees,
+ Select_PrintMachineCode,
+ Select_DebugInstTrees,
Select_DebugBurgTrees,
};
cl::opt<SelectDebugLevel_t>
@@ -497,7 +497,7 @@
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
}
-
+
bool runOnFunction(Function &F);
virtual const char *getPassName() const {
return "SparcV9 BURG Instruction Selector";
@@ -520,7 +520,7 @@
/// since the representation of int64_t and uint64_t are identical. The
/// argument can be any known const. isValidConstant is set to true if a valid
/// constant was found.
-///
+///
uint64_t ConvertConstantToIntType(const TargetMachine &target, const Value *V,
const Type *destType, bool &isValidConstant) {
isValidConstant = false;
@@ -580,7 +580,7 @@
unsigned destSize = target.getTargetData().getTypeSize(destType);
uint64_t maskHi = (destSize < 8)? (1U << 8*destSize) - 1 : ~0;
assert(opSize <= 8 && destSize <= 8 && ">8-byte int type unexpected");
-
+
if (destType->isSigned()) {
if (opSize > destSize) // operand is larger than dest:
C = C & maskHi; // mask high bits
@@ -636,7 +636,7 @@
miSETHI->getOperand(0).markHi32();
mvec.push_back(miSETHI);
}
-
+
// Set the low 10 or 12 bits in dest. This is necessary if no SETHI
// was generated, or if the low 10 bits are non-zero.
if (miSETHI==NULL || C & MAXLO) {
@@ -654,7 +654,7 @@
}
else
mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg).addMReg(SparcV9::g0).addRegDef(dest));
-
+
assert((miSETHI || miOR) && "Oops, no code was generated!");
}
@@ -663,12 +663,12 @@
/// This function correctly emulates the SETSW pseudo-op for SPARC v9. It
/// optimizes the same cases as SETUWConst, plus:
/// (1) SRA is not needed for positive or small negative values.
-///
+///
static inline void
CreateSETSWConst(int32_t C,
- Instruction* dest, std::vector<MachineInstr*>& mvec,
+ Instruction* dest, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi, Value* val) {
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg = new TmpInstruction(mcfi, (Instruction*) val);
@@ -688,44 +688,44 @@
/// left-shift-by-32 in between. This function correctly emulates the SETX
/// pseudo-op for SPARC v9. It optimizes the same cases as SETUWConst for each
/// 32 bit word.
-///
+///
static inline void
CreateSETXConst(uint64_t C,
Instruction* tmpReg, Instruction* dest,
- std::vector<MachineInstr*>& mvec,
+ std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi, Value* val) {
assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
-
+
MachineInstr* MI;
-
+
// Code to set the upper 32 bits of the value in register `tmpReg'
CreateSETUWConst((C >> 32), tmpReg, mvec, mcfi, val);
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg2 = new TmpInstruction(mcfi, (Instruction*) val);
// Shift tmpReg left by 32 bits
mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
.addRegDef(tmpReg2));
-
+
//TmpInstruction for intermediate values
TmpInstruction *tmpReg3 = new TmpInstruction(mcfi, (Instruction*) val);
// Code to set the low 32 bits of the value in register `dest'
CreateSETUWConst(C, tmpReg3, mvec, mcfi, val);
-
+
// dest = OR(tmpReg, dest)
mvec.push_back(BuildMI(V9::ORr,3).addReg(tmpReg3).addReg(tmpReg2).addRegDef(dest));
}
/// CreateSETUWLabel - Set a 32-bit constant (given by a symbolic label) in
/// the register `dest'.
-///
+///
static inline void
CreateSETUWLabel(Value* val,
Instruction* dest, std::vector<MachineInstr*>& mvec) {
MachineInstr* MI;
-
+
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get((Instruction*) val);
TmpInstruction* tmpReg = new TmpInstruction(mcfi, val);
@@ -733,7 +733,7 @@
MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(tmpReg);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
// Set the low 10 bits in dest
MI = BuildMI(V9::ORr, 3).addReg(tmpReg).addReg(val).addRegDef(dest);
MI->getOperand(1).markLo32();
@@ -742,27 +742,27 @@
/// CreateSETXLabel - Set a 64-bit constant (given by a symbolic label) in the
/// register `dest'.
-///
+///
static inline void
CreateSETXLabel(Value* val, Instruction* tmpReg,
- Instruction* dest, std::vector<MachineInstr*>& mvec,
+ Instruction* dest, std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) {
- assert(isa<Constant>(val) &&
+ assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
-
+
MachineInstr* MI;
-
+
MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
MI->getOperand(0).markHi64();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg2);
MI->getOperand(1).markLo64();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
@@ -776,12 +776,12 @@
MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg4);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
TmpInstruction* tmpReg5 =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
MI = BuildMI(V9::ORr, 3).addReg(tmpReg4).addReg(tmpReg3).addRegDef(tmpReg5);
mvec.push_back(MI);
-
+
MI = BuildMI(V9::ORi, 3).addReg(tmpReg5).addPCDisp(val).addRegDef(dest);
MI->getOperand(1).markLo32();
mvec.push_back(MI);
@@ -792,7 +792,7 @@
/// as needed. CreateSETSWConst is an optimization for the case that the
/// unsigned value has all ones in the 33 high bits (so that sign-extension sets
/// them all).
-///
+///
static inline void
CreateUIntSetInstruction(uint64_t C, Instruction* dest,
std::vector<MachineInstr*>& mvec,
@@ -813,7 +813,7 @@
/// CreateIntSetInstruction - Create code to Set a signed constant in the
/// register `dest'. Really the same as CreateUIntSetInstruction.
-///
+///
static inline void
CreateIntSetInstruction(int64_t C, Instruction* dest,
std::vector<MachineInstr*>& mvec,
@@ -824,7 +824,7 @@
/// MaxConstantsTableTy - Table mapping LLVM opcodes to the max. immediate
/// constant usable for that operation in the SparcV9 backend. Used by
/// ConstantMayNotFitInImmedField().
-///
+///
struct MaxConstantsTableTy {
// Entry == 0 ==> no immediate constant field exists at all.
// Entry > 0 ==> abs(immediate constant) <= Entry
@@ -846,10 +846,10 @@
switch(llvmOpCode) {
case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
- case Instruction::Malloc:
- case Instruction::Alloca:
- case Instruction::GetElementPtr:
- case Instruction::PHI:
+ case Instruction::Malloc:
+ case Instruction::Alloca:
+ case Instruction::GetElementPtr:
+ case Instruction::PHI:
case Instruction::Cast:
case Instruction::Call: modelOpCode = V9::ADDi; break;
@@ -901,7 +901,7 @@
/// ChooseLoadInstruction - Return the appropriate load instruction opcode
/// based on the given LLVM value type.
-///
+///
static inline MachineOpCode ChooseLoadInstruction(const Type *DestTy) {
switch (DestTy->getTypeID()) {
case Type::BoolTyID:
@@ -923,7 +923,7 @@
/// ChooseStoreInstruction - Return the appropriate store instruction opcode
/// based on the given LLVM value type.
-///
+///
static inline MachineOpCode ChooseStoreInstruction(const Type *DestTy) {
switch (DestTy->getTypeID()) {
case Type::BoolTyID:
@@ -952,9 +952,9 @@
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FADDS; break;
case Type::DoubleTyID: opCode = V9::FADDD; break;
- default: assert(0 && "Invalid type for ADD instruction"); break;
+ default: assert(0 && "Invalid type for ADD instruction"); break;
}
-
+
return opCode;
}
@@ -963,7 +963,7 @@
/// (virtual register) to a Constant* (making an immediate field), we need to
/// change the opcode from a register-based instruction to an immediate-based
/// instruction, hence this mapping.
-///
+///
static unsigned convertOpcodeFromRegToImm(unsigned Opcode) {
switch (Opcode) {
/* arithmetic */
@@ -1082,7 +1082,7 @@
// It's already in correct format
// Or, it's just not handled yet, but an assert() would break LLC
#if 0
- std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
+ std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
<< "\n";
#endif
return Opcode;
@@ -1095,20 +1095,20 @@
/// The generated instructions are returned in `mvec'. Any temp. registers
/// (TmpInstruction) created are recorded in mcfi. Any stack space required is
/// allocated via MachineFunction.
-///
+///
void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
Value* val, Instruction* dest,
std::vector<MachineInstr*>& mvec,
MachineCodeForInstruction& mcfi) {
assert(isa<Constant>(val) &&
"I only know about constant values and global addresses");
-
+
// Use a "set" instruction for known constants or symbolic constants (labels)
// that can go in an integer reg.
// We have to use a "load" instruction for all other constants,
// in particular, floating point constants.
const Type* valType = val->getType();
-
+
if (isa<GlobalValue>(val)) {
TmpInstruction* tmpReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
@@ -1131,11 +1131,11 @@
// First, create a tmp register to be used by the SETX sequence.
TmpInstruction* tmpReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
// Get the constant pool index for this constant
MachineConstantPool *CP = MachineFunction::get(F).getConstantPool();
Constant *C = cast<Constant>(val);
@@ -1143,20 +1143,20 @@
// Put the address of the constant into a register
MachineInstr* MI;
-
+
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(tmpReg);
MI->getOperand(0).markHi64();
mvec.push_back(MI);
-
+
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addConstantPoolIndex(CPI)
.addRegDef(tmpReg2);
MI->getOperand(1).markLo64();
mvec.push_back(MI);
-
+
//Create another tmp register for the SETX sequence to preserve SSA
TmpInstruction* tmpReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
@@ -1166,15 +1166,15 @@
MI = BuildMI(V9::SETHI, 2).addConstantPoolIndex(CPI).addRegDef(addrReg);
MI->getOperand(0).markHi32();
mvec.push_back(MI);
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg2 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
-
+
MI = BuildMI(V9::ORr, 3).addReg(addrReg).addReg(tmpReg3).addRegDef(addrReg2);
mvec.push_back(MI);
-
+
// Create another TmpInstruction for the address register
TmpInstruction* addrReg3 =
new TmpInstruction(mcfi, PointerType::get(val->getType()));
@@ -1197,7 +1197,7 @@
/// memory and back. The generated instructions are returned in `mvec'. Any
/// temp. virtual registers (TmpInstruction) created are recorded in mcfi.
/// Temporary stack space required is allocated via MachineFunction.
-///
+///
void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F,
Value* val, Instruction* dest,
std::vector<MachineInstr*>& mvec,
@@ -1211,14 +1211,14 @@
// FIXME: For now, we allocate permanent space because the stack frame
// manager does not allow locals to be allocated (e.g., for alloca) after
// a temp is allocated!
- int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
+ int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
unsigned FPReg = target.getRegInfo()->getFramePointer();
// Store instruction stores `val' to [%fp+offset].
// The store opCode is based only the source value being copied.
unsigned StoreOpcode = ChooseStoreInstruction(opTy);
- StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
+ StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
mvec.push_back(BuildMI(StoreOpcode, 3)
.addReg(val).addMReg(FPReg).addSImm(offset));
@@ -1238,7 +1238,7 @@
/// CreateBitExtensionInstructions - Helper function for sign-extension and
/// zero-extension. For SPARC v9, we sign-extend the given operand using SLL;
/// SRA/SRL.
-///
+///
inline void
CreateBitExtensionInstructions(bool signExtend, const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
@@ -1267,7 +1267,7 @@
/// in bits, not bytes). The generated instructions are returned in `mvec'. Any
/// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
/// space required is allocated via MachineFunction.
-///
+///
void CreateSignExtensionInstructions(const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
unsigned int numLowBits,
@@ -1283,7 +1283,7 @@
/// SLL; SRL. The generated instructions are returned in `mvec'. Any temp.
/// registers (TmpInstruction) created are recorded in mcfi. Any stack space
/// required is allocated via MachineFunction.
-///
+///
void CreateZeroExtensionInstructions(const TargetMachine& target,
Function* F, Value* srcVal, Value* destVal,
unsigned int numLowBits,
@@ -1312,7 +1312,7 @@
// Get a stack slot to use for the copy
int offset = MachineFunction::get(F).getInfo<SparcV9FunctionInfo>()->allocateLocalVar(val);
- // Get the size of the source value being copied.
+ // Get the size of the source value being copied.
size_t srcSize = target.getTargetData().getTypeSize(val->getType());
// Store instruction stores `val' to [%fp+offset].
@@ -1352,7 +1352,7 @@
/// InsertCodeToLoadConstant - Generates code to load the constant
/// into a TmpInstruction (virtual reg) and returns the virtual register.
-///
+///
static TmpInstruction*
InsertCodeToLoadConstant(Function *F, Value* opValue, Instruction* vmInstr,
std::vector<MachineInstr*>& loadConstVec,
@@ -1360,12 +1360,12 @@
// Create a tmp virtual register to hold the constant.
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(vmInstr);
TmpInstruction* tmpReg = new TmpInstruction(mcfi, opValue);
-
+
CreateCodeToLoadConst(target, F, opValue, tmpReg, loadConstVec, mcfi);
-
+
// Record the mapping from the tmp VM instruction to machine instruction.
// Do this for all machine instructions that were not mapped to any
- // other temp values created by
+ // other temp values created by
// tmpReg->addMachineInstruction(loadConstVec.back());
return tmpReg;
}
@@ -1419,7 +1419,7 @@
/// for arbitrary types. The generated instructions are returned in `mvec'. Any
/// temp. registers (TmpInstruction) created are recorded in mcfi. Any stack
/// space required is allocated via MachineFunction.
-///
+///
void CreateCopyInstructionsByType(const TargetMachine& target,
Function *F, Value* src, Instruction* dest,
std::vector<MachineInstr*>& mvec,
@@ -1441,16 +1441,16 @@
MachineOperand::MachineOperandType opType =
ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
machineRegNum, immedValue);
-
+
if (opType == MachineOperand::MO_VirtualRegister)
loadConstantToReg = true;
}
-
- if (loadConstantToReg) {
+
+ if (loadConstantToReg) {
// `src' is constant and cannot fit in immed field for the ADD.
// Insert instructions to "load" the constant into a register.
CreateCodeToLoadConst(target, F, src, dest, mvec, mcfi);
- } else {
+ } else {
// Create a reg-to-reg copy instruction for the given type:
// -- For FP values, create a FMOVS or FMOVD instruction
// -- For non-FP values, create an add-with-0 instruction (opCode as above)
@@ -1476,12 +1476,12 @@
/// pool. In the first 2 cases, the operand of `minstr' is modified in place.
/// Returns a vector of machine instructions generated for operands that fall
/// under case 3; these must be inserted before `minstr'.
-///
+///
std::vector<MachineInstr*>
FixConstantOperandsForInstr(Instruction* vmInstr, MachineInstr* minstr,
TargetMachine& target) {
std::vector<MachineInstr*> MVec;
-
+
MachineOpCode opCode = minstr->getOpcode();
const TargetInstrInfo& instrInfo = *target.getInstrInfo();
int resultPos = instrInfo.get(opCode).resultPos;
@@ -1491,7 +1491,7 @@
for (unsigned op=0; op < minstr->getNumOperands(); op++) {
const MachineOperand& mop = minstr->getOperand(op);
-
+
// Skip the result position, preallocated machine registers, or operands
// that cannot be constants (CC regs or PC-relative displacements)
if (resultPos == (int)op ||
@@ -1511,7 +1511,7 @@
if (mop.getType() == MachineOperand::MO_VirtualRegister) {
assert(mop.getVRegValue() != NULL);
opValue = mop.getVRegValue();
- if (Constant *opConst = dyn_cast<Constant>(opValue))
+ if (Constant *opConst = dyn_cast<Constant>(opValue))
if (!isa<GlobalValue>(opConst)) {
opType = ChooseRegOrImmed(opConst, opCode, target,
(immedPos == (int)op), machineRegNum,
@@ -1534,7 +1534,7 @@
continue;
opType = ChooseRegOrImmed(mop.getImmedValue(), isSigned,
- opCode, target, (immedPos == (int)op),
+ opCode, target, (immedPos == (int)op),
machineRegNum, immedValue);
if (opType == MachineOperand::MO_SignExtendedImmed ||
@@ -1545,7 +1545,7 @@
minstr->setOpcode(newOpcode);
}
- if (opType == mop.getType())
+ if (opType == mop.getType())
continue; // no change: this is the most common case
if (opType == MachineOperand::MO_VirtualRegister) {
@@ -1575,7 +1575,7 @@
tmpReg);
}
}
-
+
// Also, check for implicit operands used by the machine instruction
// (no need to check those defined since they cannot be constants).
// These include:
@@ -1590,14 +1590,14 @@
CallArgsDescriptor* argDesc = NULL; // unused if not a call
if (isCall)
argDesc = CallArgsDescriptor::get(minstr);
-
+
for (unsigned i=0, N=minstr->getNumImplicitRefs(); i < N; ++i)
if (isa<Constant>(minstr->getImplicitRef(i))) {
Value* oldVal = minstr->getImplicitRef(i);
TmpInstruction* tmpReg =
InsertCodeToLoadConstant(F, oldVal, vmInstr, MVec, target);
minstr->setImplicitRef(i, tmpReg);
-
+
if (isCall) {
// find and replace the argument in the CallArgsDescriptor
unsigned i=lastCallArgNum;
@@ -1609,7 +1609,7 @@
argDesc->getArgInfo(i).replaceArgVal(tmpReg);
}
}
-
+
return MVec;
}
@@ -1705,7 +1705,7 @@
// If the first getElementPtr instruction had a leading [0], add it back.
// Note that this instruction is the *last* one that was successfully
// folded *and* contributed any indices, in the loop above.
- if (ptrVal && ! lastInstHasLeadingNonZero)
+ if (ptrVal && ! lastInstHasLeadingNonZero)
chainIdxVec.insert(chainIdxVec.begin(), ConstantSInt::get(Type::LongTy,0));
return ptrVal;
@@ -1724,7 +1724,7 @@
// Default pointer is the one from the current instruction.
Value* ptrVal = gepI->getPointerOperand();
- InstrTreeNode* ptrChild = gepNode->leftChild();
+ InstrTreeNode* ptrChild = gepNode->leftChild();
// Extract the index vector of the GEP instruction.
// If all indices are constant and first index is zero, try to fold
@@ -1761,7 +1761,7 @@
/// no code is generated for them. Returns the pointer Value to use, and
/// returns the resulting IndexVector in idxVec. Sets allConstantIndices
/// to true/false if all indices are/aren't const.
-///
+///
static Value *GetMemInstArgs(InstructionNode *memInstrNode,
std::vector<Value*> &idxVec,
bool& allConstantIndices) {
@@ -1774,10 +1774,10 @@
// right child for Store instructions.
InstrTreeNode* ptrChild = (memInst->getOpcode() == Instruction::Store
? memInstrNode->rightChild()
- : memInstrNode->leftChild());
-
+ : memInstrNode->leftChild());
+
// Default pointer is the one from the current instruction.
- Value* ptrVal = ptrChild->getValue();
+ Value* ptrVal = ptrChild->getValue();
// Find the "last" GetElemPtr instruction: this one or the immediate child.
// There will be none if this is a load or a store from a scalar pointer.
@@ -1797,13 +1797,13 @@
: ptrVal;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBprInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode;
-
+
Instruction* setCCInstr =
((InstructionNode*) instrNode->leftChild())->getInstruction();
-
+
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::BRZ; break;
case Instruction::SetNE: opCode = V9::BRNZ; break;
@@ -1814,19 +1814,19 @@
default:
assert(0 && "Unrecognized VM instruction!");
opCode = V9::INVALID_OPCODE;
- break;
+ break;
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
-
+
if (isSigned) {
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::BE; break;
@@ -1837,7 +1837,7 @@
case Instruction::SetGT: opCode = V9::BG; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
} else {
switch(setCCInstr->getOpcode()) {
@@ -1849,18 +1849,18 @@
case Instruction::SetGT: opCode = V9::BGU; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBFpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(setCCInstr->getOpcode()) {
case Instruction::SetEQ: opCode = V9::FBE; break;
case Instruction::SetNE: opCode = V9::FBNE; break;
@@ -1870,9 +1870,9 @@
case Instruction::SetGT: opCode = V9::FBG; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
-
+
return opCode;
}
@@ -1883,37 +1883,37 @@
// into a separate class that can hold such information.
// The static cache is not too bad because the memory for these
// TmpInstructions will be freed along with the rest of the Function anyway.
-//
+//
static TmpInstruction *GetTmpForCC (Value* boolVal, const Function *F,
const Type* ccType,
MachineCodeForInstruction& mcfi) {
typedef hash_map<const Value*, TmpInstruction*> BoolTmpCache;
static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
static const Function *lastFunction = 0;// Use to flush cache between funcs
-
+
assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
-
+
if (lastFunction != F) {
lastFunction = F;
boolToTmpCache.clear();
}
-
+
// Look for tmpI and create a new one otherwise. The new value is
// directly written to map using the ref returned by operator[].
TmpInstruction*& tmpI = boolToTmpCache[boolVal];
if (tmpI == NULL)
tmpI = new TmpInstruction(mcfi, ccType, boolVal);
-
+
return tmpI;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseBccInstruction(const InstructionNode* instrNode, const Type*& setCCType) {
InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
assert(setCCNode->getOpLabel() == SetCCOp);
BinaryOperator* setCCInstr =cast<BinaryOperator>(setCCNode->getInstruction());
setCCType = setCCInstr->getOperand(0)->getType();
-
+
if (setCCType->isFloatingPoint())
return ChooseBFpccInstruction(instrNode, setCCInstr);
else
@@ -1926,11 +1926,11 @@
/// two registers is required, then modify this function and use
/// convertOpcodeFromRegToImm() where required. It will be necessary to expand
/// convertOpcodeFromRegToImm() to handle the new cases of opcodes.
-///
-static inline MachineOpCode
+///
+static inline MachineOpCode
ChooseMovFpcciInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVFEi; break;
case Instruction::SetNE: opCode = V9::MOVFNEi; break;
@@ -1940,25 +1940,25 @@
case Instruction::SetGT: opCode = V9::MOVFGi; break;
default:
assert(0 && "Unrecognized VM instruction!");
- break;
+ break;
}
-
+
return opCode;
}
/// ChooseMovpcciForSetCC -- Choose a conditional-move instruction
/// based on the type of SetCC operation.
-///
+///
/// WARNING: like the previous function, this function always returns
/// the opcode that expects an immediate and a register. See above.
-///
+///
static MachineOpCode ChooseMovpcciForSetCC(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
const Type* opType = instrNode->leftChild()->getValue()->getType();
assert(opType->isIntegral() || isa<PointerType>(opType));
bool noSign = opType->isUnsigned() || isa<PointerType>(opType);
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVEi; break;
case Instruction::SetLE: opCode = noSign? V9::MOVLEUi : V9::MOVLEi; break;
@@ -1966,22 +1966,22 @@
case Instruction::SetLT: opCode = noSign? V9::MOVCSi : V9::MOVLi; break;
case Instruction::SetGT: opCode = noSign? V9::MOVGUi : V9::MOVGi; break;
case Instruction::SetNE: opCode = V9::MOVNEi; break;
- default: assert(0 && "Unrecognized LLVM instr!"); break;
+ default: assert(0 && "Unrecognized LLVM instr!"); break;
}
-
+
return opCode;
}
/// ChooseMovpregiForSetCC -- Choose a conditional-move-on-register-value
/// instruction based on the type of SetCC operation. These instructions
/// compare a register with 0 and perform the move is the comparison is true.
-///
+///
/// WARNING: like the previous function, this function it always returns
/// the opcode that expects an immediate and a register. See above.
-///
+///
static MachineOpCode ChooseMovpregiForSetCC(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
switch(instrNode->getInstruction()->getOpcode()) {
case Instruction::SetEQ: opCode = V9::MOVRZi; break;
case Instruction::SetLE: opCode = V9::MOVRLEZi; break;
@@ -1989,9 +1989,9 @@
case Instruction::SetLT: opCode = V9::MOVRLZi; break;
case Instruction::SetGT: opCode = V9::MOVRGZi; break;
case Instruction::SetNE: opCode = V9::MOVRNZi; break;
- default: assert(0 && "Unrecognized VM instr!"); break;
+ default: assert(0 && "Unrecognized VM instr!"); break;
}
-
+
return opCode;
}
@@ -2018,11 +2018,11 @@
assert(opSize == 8 && "Unrecognized type size > 4 and < 8!");
opCode = (vopCode == ToFloatTy? V9::FXTOS : V9::FXTOD);
}
-
+
return opCode;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseConvertFPToIntInstr(const TargetMachine& target,
const Type* destType, const Type* opType) {
assert((opType == Type::FloatTy || opType == Type::DoubleTy)
@@ -2063,7 +2063,7 @@
/// MAXUNSIGNED (i.e., 2^31 <= V <= 2^32-1) would be converted incorrectly.
/// Therefore, for converting an FP value to uint32_t, we first need to convert
/// to uint64_t and then to uint32_t.
-///
+///
static void
CreateCodeToConvertFloatToInt(const TargetMachine& target,
Value* opVal, Instruction* destI,
@@ -2108,12 +2108,12 @@
/*numLowBits*/ 32, mvec, mcfi);
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseAddInstruction(const InstructionNode* instrNode) {
return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateMovFloatInstruction(const InstructionNode* instrNode,
const Type* resultType) {
return BuildMI((resultType == Type::FloatTy) ? V9::FMOVS : V9::FMOVD, 2)
@@ -2121,13 +2121,13 @@
.addRegDef(instrNode->getValue());
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateAddConstInstruction(const InstructionNode* instrNode) {
MachineInstr* minstr = NULL;
-
+
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
assert(isa<Constant>(constOp));
-
+
// Cases worth optimizing are:
// (1) Add with 0 for float or double: use an FMOV of appropriate type,
// instead of an FADD (1 vs 3 cycles). There is no integer MOV.
@@ -2137,33 +2137,33 @@
minstr = CreateMovFloatInstruction(instrNode,
instrNode->getInstruction()->getType());
}
-
+
return minstr;
}
static inline MachineOpCode ChooseSubInstructionByType(const Type* resultType) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
if (resultType->isInteger() || isa<PointerType>(resultType)) {
opCode = V9::SUBr;
} else {
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FSUBS; break;
case Type::DoubleTyID: opCode = V9::FSUBD; break;
- default: assert(0 && "Invalid type for SUB instruction"); break;
+ default: assert(0 && "Invalid type for SUB instruction"); break;
}
}
return opCode;
}
-static inline MachineInstr*
+static inline MachineInstr*
CreateSubConstInstruction(const InstructionNode* instrNode) {
MachineInstr* minstr = NULL;
-
+
Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
assert(isa<Constant>(constOp));
-
+
// Cases worth optimizing are:
// (1) Sub with 0 for float or double: use an FMOV of appropriate type,
// instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
@@ -2173,27 +2173,27 @@
minstr = CreateMovFloatInstruction(instrNode,
instrNode->getInstruction()->getType());
}
-
+
return minstr;
}
-static inline MachineOpCode
+static inline MachineOpCode
ChooseFcmpInstruction(const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
switch(operand->getType()->getTypeID()) {
case Type::FloatTyID: opCode = V9::FCMPS; break;
case Type::DoubleTyID: opCode = V9::FCMPD; break;
- default: assert(0 && "Invalid type for FCMP instruction"); break;
+ default: assert(0 && "Invalid type for FCMP instruction"); break;
}
-
+
return opCode;
}
/// BothFloatToDouble - Assumes that leftArg and rightArg of instrNode are both
/// cast instructions. Returns true if both are floats cast to double.
-///
+///
static inline bool BothFloatToDouble(const InstructionNode* instrNode) {
InstrTreeNode* leftArg = instrNode->leftChild();
InstrTreeNode* rightArg = instrNode->rightChild();
@@ -2207,16 +2207,16 @@
static inline MachineOpCode ChooseMulInstructionByType(const Type* resultType) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
if (resultType->isInteger())
opCode = V9::MULXr;
else
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FMULS; break;
case Type::DoubleTyID: opCode = V9::FMULD; break;
- default: assert(0 && "Invalid type for MUL instruction"); break;
+ default: assert(0 && "Invalid type for MUL instruction"); break;
}
-
+
return opCode;
}
@@ -2233,7 +2233,7 @@
/// significant bit of the operand after shifting (e.g., bit 32 of Int or bit 16
/// of Short), so we do not have to worry about results that are as large as a
/// normal integer register.
-///
+///
static inline void
CreateShiftInstructions(const TargetMachine& target, Function* F,
MachineOpCode shiftOpCode, Value* argVal1,
@@ -2244,7 +2244,7 @@
assert((optArgVal2 != NULL || optShiftNum <= 64) &&
"Large shift sizes unexpected, but can be handled below: "
"You need to check whether or not it fits in immed field below");
-
+
// If this is a logical left shift of a type smaller than the standard
// integer reg. size, we have to extend the sign-bit into upper bits
// of dest, so we need to put the result of the SLL into a temporary.
@@ -2255,14 +2255,14 @@
// put SLL result into a temporary
shiftDest = new TmpInstruction(mcfi, argVal1, optArgVal2, "sllTmp");
}
-
+
MachineInstr* M = (optArgVal2 != NULL)
? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
.addReg(shiftDest, MachineOperand::Def)
: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
.addReg(shiftDest, MachineOperand::Def);
mvec.push_back(M);
-
+
if (shiftDest != destVal) {
// extend the sign-bit of the result into all upper bits of dest
assert(8*opSize <= 32 && "Unexpected type size > 4 and < IntRegSize?");
@@ -2275,7 +2275,7 @@
/// cannot exploit constant to create a cheaper instruction. This returns the
/// approximate cost of the instructions generated, which is used to pick the
/// cheapest when both operands are constant.
-///
+///
static unsigned
CreateMulConstInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
@@ -2284,16 +2284,16 @@
// Use max. multiply cost, viz., cost of MULX
unsigned cost = target.getInstrInfo()->minLatency(V9::MULXr);
unsigned firstNewInstr = mvec.size();
-
+
Value* constOp = rval;
if (! isa<Constant>(constOp))
return cost;
-
+
// Cases worth optimizing are:
// (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
// (2) Multiply by 2^x for integer types: replace with Shift
const Type* resultType = destVal->getType();
-
+
if (resultType->isInteger() || isa<PointerType>(resultType)) {
bool isValidConst;
int64_t C = (int64_t) ConvertConstantToIntType(target, constOp,
@@ -2306,7 +2306,7 @@
needNeg = true;
C = -C;
}
-
+
if (C == 0 || C == 1) {
cost = target.getInstrInfo()->minLatency(V9::ADDr);
unsigned Zero = target.getRegInfo()->getZeroRegNum();
@@ -2322,7 +2322,7 @@
CreateShiftInstructions(target, F, opCode, lval, NULL, pow,
destVal, mvec, mcfi);
}
-
+
if (mvec.size() > 0 && needNeg) {
// insert <reg = SUB 0, reg> after the instr to flip the sign
MachineInstr* M = CreateIntNegInstruction(target, destVal);
@@ -2337,16 +2337,16 @@
? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
: (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
mvec.push_back(BuildMI(opCode,2).addReg(lval).addRegDef(destVal));
- }
+ }
}
}
-
+
if (firstNewInstr < mvec.size()) {
cost = 0;
for (unsigned i=firstNewInstr; i < mvec.size(); ++i)
cost += target.getInstrInfo()->minLatency(mvec[i]->getOpcode());
}
-
+
return cost;
}
@@ -2371,14 +2371,14 @@
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
else if (isa<Constant>(lval)) // lval is constant, but not rval
CreateMulConstInstruction(target, F, lval, rval, destVal, mvec, mcfi);
-
+
// else neither is constant
return;
}
/// CreateMulInstruction - Returns NULL if we cannot exploit constant
/// to create a cheaper instruction.
-///
+///
static inline void
CreateMulInstruction(const TargetMachine &target, Function* F,
Value* lval, Value* rval, Instruction* destVal,
@@ -2392,7 +2392,7 @@
// Use FSMULD if both operands are actually floats cast to doubles.
// Otherwise, use the default opcode for the appropriate type.
MachineOpCode mulOp = ((forceMulOp != -1)
- ? forceMulOp
+ ? forceMulOp
: ChooseMulInstructionByType(destVal->getType()));
mvec.push_back(BuildMI(mulOp, 3).addReg(lval).addReg(rval)
.addRegDef(destVal));
@@ -2402,28 +2402,28 @@
/// ChooseDivInstruction - Generate a divide instruction for Div or Rem.
/// For Rem, this assumes that the operand type will be signed if the result
/// type is signed. This is correct because they must have the same sign.
-///
-static inline MachineOpCode
+///
+static inline MachineOpCode
ChooseDivInstruction(TargetMachine &target, const InstructionNode* instrNode) {
MachineOpCode opCode = V9::INVALID_OPCODE;
-
+
const Type* resultType = instrNode->getInstruction()->getType();
-
+
if (resultType->isInteger())
opCode = resultType->isSigned()? V9::SDIVXr : V9::UDIVXr;
else
switch(resultType->getTypeID()) {
case Type::FloatTyID: opCode = V9::FDIVS; break;
case Type::DoubleTyID: opCode = V9::FDIVD; break;
- default: assert(0 && "Invalid type for DIV instruction"); break;
+ default: assert(0 && "Invalid type for DIV instruction"); break;
}
-
+
return opCode;
}
/// CreateDivConstInstruction - Return if we cannot exploit constant to create
/// a cheaper instruction.
-///
+///
static void CreateDivConstInstruction(TargetMachine &target,
const InstructionNode* instrNode,
std::vector<MachineInstr*>& mvec) {
@@ -2434,12 +2434,12 @@
Instruction* destVal = instrNode->getInstruction();
unsigned ZeroReg = target.getRegInfo()->getZeroRegNum();
-
+
// Cases worth optimizing are:
// (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
// (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
const Type* resultType = instrNode->getInstruction()->getType();
-
+
if (resultType->isInteger()) {
unsigned pow;
bool isValidConst;
@@ -2452,7 +2452,7 @@
needNeg = true;
C = -C;
}
-
+
if (C == 1) {
mvec.push_back(BuildMI(V9::ADDr, 3).addReg(LHS).addMReg(ZeroReg)
.addRegDef(destVal));
@@ -2464,16 +2464,16 @@
if (resultType->isSigned()) {
// For N / 2^k, if the operand N is negative,
// we need to add (2^k - 1) before right-shifting by k, i.e.,
- //
+ //
// (N / 2^k) = N >> k, if N >= 0;
// (N + 2^k - 1) >> k, if N < 0
- //
+ //
// If N is <= 32 bits, use:
// sra N, 31, t1 // t1 = ~0, if N < 0, 0 else
// srl t1, 32-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
// add t2, N, t3 // t3 = N + 2^k -1, if N < 0, N else
// sra t3, k, result // result = N / 2^k
- //
+ //
// If N is 64 bits, use:
// srax N, k-1, t1 // t1 = sign bit in high k positions
// srlx t1, 64-k, t2 // t2 = 2^k - 1, if N < 0, 0 else
@@ -2515,7 +2515,7 @@
mvec.push_back(BuildMI(opCode, 3).addReg(shiftOperand).addZImm(pow)
.addRegDef(destVal));
}
-
+
if (needNeg && (C == 1 || isPowerOf2(C, pow))) {
// insert <reg = SUB 0, reg> after the instr to flip the sign
mvec.push_back(CreateIntNegInstruction(target, destVal));
@@ -2525,12 +2525,12 @@
if (ConstantFP *FPC = dyn_cast<ConstantFP>(constOp)) {
double dval = FPC->getValue();
if (fabs(dval) == 1) {
- unsigned opCode =
+ unsigned opCode =
(dval < 0) ? (resultType == Type::FloatTy? V9::FNEGS : V9::FNEGD)
: (resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD);
-
+
mvec.push_back(BuildMI(opCode, 2).addReg(LHS).addRegDef(destVal));
- }
+ }
}
}
}
@@ -2604,7 +2604,7 @@
// Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
getMvec.push_back(BuildMI(V9::ADDr,3).addMReg(SPReg).addReg(dynamicAreaOffset)
.addRegDef(result));
-}
+}
static void
CreateCodeForFixedSizeAlloca(const TargetMachine& target,
@@ -2629,7 +2629,7 @@
// spills, and temporaries to have large offsets.
// NOTE: We use LARGE = 8 * argSlotSize = 64 bytes.
// You've gotta love having only 13 bits for constant offset values :-|.
- //
+ //
unsigned paddedSize;
int offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->computeOffsetforLocalVar(result,
paddedSize,
@@ -2637,19 +2637,19 @@
if (((int)paddedSize) > 8 * SparcV9FrameInfo::SizeOfEachArgOnStack ||
!target.getInstrInfo()->constantFitsInImmedField(V9::LDXi,offsetFromFP)) {
- CreateCodeForVariableSizeAlloca(target, result, tsize,
+ CreateCodeForVariableSizeAlloca(target, result, tsize,
ConstantSInt::get(Type::IntTy,numElements),
getMvec);
return;
}
-
+
// else offset fits in immediate field so go ahead and allocate it.
offsetFromFP = mcInfo.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(result, tsize *numElements);
-
+
// Create a temporary Value to hold the constant offset.
// This is needed because it may not fit in the immediate field.
ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
-
+
// Instruction 1: add %fp, offsetFromFP -> result
unsigned FPReg = target.getRegInfo()->getFramePointer();
getMvec.push_back(BuildMI(V9::ADDr, 3).addMReg(FPReg).addReg(offsetVal)
@@ -2685,10 +2685,10 @@
MachineOperand::MO_VirtualRegister;
// Check if there is an index vector and if so, compute the
- // right offset for structures and for arrays
+ // right offset for structures and for arrays
if (!idxVec.empty()) {
const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
-
+
// If all indices are constant, compute the combined offset directly.
if (allConstantIndices) {
// Compute the offset value using the index vector. Create a
@@ -2701,7 +2701,7 @@
// offset. (An extra leading zero offset, if any, can be ignored.)
// Generate code sequence to compute address from index.
bool firstIdxIsZero = IsZero(idxVec[0]);
- assert(idxVec.size() == 1U + firstIdxIsZero
+ assert(idxVec.size() == 1U + firstIdxIsZero
&& "Array refs must be lowered before Instruction Selection");
Value* idxVal = idxVec[firstIdxIsZero];
@@ -2732,7 +2732,7 @@
assert(mulVec.size() > 0 && "No multiply code created?");
mvec.insert(mvec.end(), mulVec.begin(), mulVec.end());
-
+
valueForRegOffset = addr;
}
} else {
@@ -2773,11 +2773,11 @@
/// Check both explicit and implicit operands! Also make sure to skip over a
/// parent who: (1) is a list node in the Burg tree, or (2) itself had its
/// results forwarded to its parent.
-///
+///
static void ForwardOperand (InstructionNode *treeNode, InstrTreeNode *parent,
int operandNum) {
assert(treeNode && parent && "Invalid invocation of ForwardOperand");
-
+
Instruction* unusedOp = treeNode->getInstruction();
Value* fwdOp = unusedOp->getOperand(operandNum);
@@ -2787,7 +2787,7 @@
assert(parent && "ERROR: Non-instruction node has no parent in tree.");
}
InstructionNode* parentInstrNode = (InstructionNode*) parent;
-
+
Instruction* userInstr = parentInstrNode->getInstruction();
MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
@@ -2809,7 +2809,7 @@
fwdOp);
}
}
-
+
for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
if (minstr->getImplicitRef(i) == unusedOp)
minstr->setImplicitRef(i, fwdOp);
@@ -2819,7 +2819,7 @@
/// AllUsesAreBranches - Returns true if all the uses of I are
/// Branch instructions, false otherwise.
-///
+///
inline bool AllUsesAreBranches(const Instruction* I) {
for (Value::use_const_iterator UI=I->use_begin(), UE=I->use_end();
UI != UE; ++UI)
@@ -2832,7 +2832,7 @@
/// CodeGenIntrinsic - Generate code for any intrinsic that needs a special
/// code sequence instead of a regular call. If not that kind of intrinsic, do
/// nothing. Returns true if code was generated, otherwise false.
-///
+///
static bool CodeGenIntrinsic(Intrinsic::ID iid, CallInst &callInstr,
TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
@@ -2844,7 +2844,7 @@
Function* func = cast<Function>(callInstr.getParent()->getParent());
int numFixedArgs = func->getFunctionType()->getNumParams();
int fpReg = SparcV9::i6;
- int firstVarArgOff = numFixedArgs * 8 +
+ int firstVarArgOff = numFixedArgs * 8 +
SparcV9FrameInfo::FirstIncomingArgOffsetFromFP;
mvec.push_back(BuildMI(V9::ADDi, 3).addMReg(fpReg).addSImm(firstVarArgOff).
addRegDef(&callInstr));
@@ -2865,7 +2865,7 @@
}
/// ThisIsAChainRule - returns true if the given BURG rule is a chain rule.
-///
+///
extern bool ThisIsAChainRule(int eruleno) {
switch(eruleno) {
case 111: // stmt: reg
@@ -2899,7 +2899,7 @@
/// GetInstructionsByRule - Choose machine instructions for the
/// SPARC V9 according to the patterns chosen by the BURG-generated parser.
/// This is where most of the work in the V9 instruction selector gets done.
-///
+///
void GetInstructionsByRule(InstructionNode* subtreeRoot, int ruleForNode,
short* nts, TargetMachine &target,
std::vector<MachineInstr*>& mvec) {
@@ -2912,13 +2912,13 @@
unsigned L;
bool foldCase = false;
- mvec.clear();
-
+ mvec.clear();
+
// If the code for this instruction was folded into the parent (user),
// then do nothing!
if (subtreeRoot->isFoldedIntoParent())
return;
-
+
// Let's check for chain rules outside the switch so that we don't have
// to duplicate the list of chain rule production numbers here again
if (ThisIsAChainRule(ruleForNode)) {
@@ -2948,10 +2948,10 @@
// used by the machine instruction but not represented in LLVM.
Instruction* returnAddrTmp = new TmpInstruction(mcfi, returnInstr);
- MachineInstr* retMI =
+ MachineInstr* retMI =
BuildMI(V9::JMPLRETi, 3).addReg(returnAddrTmp).addSImm(8)
.addMReg(target.getRegInfo()->getZeroRegNum(), MachineOperand::Def);
-
+
// If there is a value to return, we need to:
// (a) Sign-extend the value if it is smaller than 8 bytes (reg size)
// (b) Insert a copy to copy the return value to the appropriate reg.
@@ -2987,11 +2987,11 @@
// -- For non-FP values, create an add-with-0 instruction
// First, create a virtual register to represent the register and
// mark this vreg as being an implicit operand of the ret MI.
- TmpInstruction* retVReg =
+ TmpInstruction* retVReg =
new TmpInstruction(mcfi, retValToUse, NULL, "argReg");
-
+
retMI->addImplicitRef(retVReg);
-
+
if (retType->isFloatingPoint())
M = (BuildMI(retType==Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
.addReg(retValToUse).addReg(retVReg, MachineOperand::Def));
@@ -3006,14 +3006,14 @@
mvec.push_back(M);
}
-
+
// Now insert the RET instruction and a NOP for the delay slot
mvec.push_back(retMI);
mvec.push_back(BuildMI(V9::NOP, 0));
-
+
break;
- }
-
+ }
+
case 3: // stmt: Store(reg,reg)
case 4: // stmt: Store(reg,ptrreg)
SetOperandsForMemInstr(ChooseStoreInstruction(
@@ -3025,7 +3025,7 @@
{
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(0)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
@@ -3036,13 +3036,13 @@
// If the constant is ZERO, we can use the branch-on-integer-register
// instructions and avoid the SUBcc instruction entirely.
// Otherwise this is just the same as case 5, so just fall through.
- //
+ //
InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
assert(constNode &&
constNode->getNodeType() ==InstrTreeNode::NTConstNode);
Constant *constVal = cast<Constant>(constNode->getValue());
bool isValidConst;
-
+
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
&& ConvertConstantToIntType(target,
@@ -3056,21 +3056,21 @@
subtreeRoot->leftChild();
assert(setCCNode->getOpLabel() == SetCCOp);
setCCNode->markFoldedIntoParent();
-
+
BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
-
+
M = BuildMI(ChooseBprInstruction(subtreeRoot), 2)
.addReg(setCCNode->leftChild()->getValue())
.addPCDisp(brInst->getSuccessor(0));
mvec.push_back(M);
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
// false branch
mvec.push_back(BuildMI(V9::BA, 1)
.addPCDisp(brInst->getSuccessor(1)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
@@ -3083,7 +3083,7 @@
// The branch to use depends on whether it is FP, signed, or unsigned.
// If it is an integer CC, we also need to find the unique
// TmpInstruction representing that CC.
- //
+ //
BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
const Type* setCCType;
unsigned Opcode = ChooseBccInstruction(subtreeRoot, setCCType);
@@ -3105,27 +3105,27 @@
mvec.push_back(BuildMI(V9::NOP, 0));
break;
}
-
+
case 208: // stmt: BrCond(boolconst)
{
// boolconst => boolean is a constant; use BA to first or second label
- Constant* constVal =
+ Constant* constVal =
cast<Constant>(subtreeRoot->leftChild()->getValue());
unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
-
+
M = BuildMI(V9::BA, 1).addPCDisp(
cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(dest));
mvec.push_back(M);
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
}
-
+
case 8: // stmt: BrCond(boolreg)
{ // boolreg => boolean is recorded in an integer register.
// Use branch-on-integer-register instruction.
- //
+ //
BranchInst *BI = cast<BranchInst>(subtreeRoot->getInstruction());
M = BuildMI(V9::BRNZ, 2).addReg(subtreeRoot->leftChild()->getValue())
.addPCDisp(BI->getSuccessor(0));
@@ -3136,12 +3136,12 @@
// false branch
mvec.push_back(BuildMI(V9::BA, 1).addPCDisp(BI->getSuccessor(1)));
-
+
// delay slot
mvec.push_back(BuildMI(V9::NOP, 0));
break;
- }
-
+ }
+
case 9: // stmt: Switch(reg)
assert(0 && "*** SWITCH instruction is not implemented yet.");
break;
@@ -3191,7 +3191,7 @@
MachineCodeForInstruction &mcfi = MachineCodeForInstruction::get(castI);
TmpInstruction* tempReg =
new TmpInstruction(mcfi, opVal);
-
+
assert(opVal->getType()->isIntegral() ||
@@ -3209,7 +3209,7 @@
break;
}
-
+
case 23: // reg: ToUByteTy(reg)
case 24: // reg: ToSByteTy(reg)
case 25: // reg: ToUShortTy(reg)
@@ -3221,7 +3221,7 @@
{
//======================================================================
// Rules for integer conversions:
- //
+ //
//--------
// From ISO 1998 C++ Standard, Sec. 4.7:
//
@@ -3231,21 +3231,21 @@
// unsigned type). [Note: In a two s complement representation,
// this conversion is conceptual and there is no change in the
// bit pattern (if there is no truncation). ]
- //
+ //
// 3. If the destination type is signed, the value is unchanged if
// it can be represented in the destination type (and bitfield width);
// otherwise, the value is implementation-defined.
//--------
- //
+ //
// Since we assume 2s complement representations, this implies:
- //
+ //
// -- If operand is smaller than destination, zero-extend or sign-extend
// according to the signedness of the *operand*: source decides:
// (1) If operand is signed, sign-extend it.
// If dest is unsigned, zero-ext the result!
// (2) If operand is unsigned, our current invariant is that
// it's high bits are correct, so zero-extension is not needed.
- //
+ //
// -- If operand is same size as or larger than destination,
// zero-extend or sign-extend according to the signedness of
// the *destination*: destination decides:
@@ -3264,7 +3264,7 @@
const Type* destType = destI->getType();
unsigned opSize = target.getTargetData().getTypeSize(opType);
unsigned destSize = target.getTargetData().getTypeSize(destType);
-
+
bool isIntegral = opType->isIntegral() || isa<PointerType>(opType);
if (opType == Type::BoolTy ||
@@ -3322,17 +3322,17 @@
break;
}
-
+
case 31: // reg: ToFloatTy(reg):
case 32: // reg: ToDoubleTy(reg):
case 232: // reg: ToDoubleTy(Constant):
-
- // If this instruction has a parent (a user) in the tree
+
+ // If this instruction has a parent (a user) in the tree
// and the user is translated as an FsMULd instruction,
// then the cast is unnecessary. So check that first.
// In the future, we'll want to do the same for the FdMULq instruction,
// so do the check here instead of only for ToFloatTy(reg).
- //
+ //
if (subtreeRoot->parent() != NULL) {
const MachineCodeForInstruction& mcfi =
MachineCodeForInstruction::get(
@@ -3360,12 +3360,12 @@
// The type of this temporary will determine the FP
// register used: single-prec for a 32-bit int or smaller,
// double-prec for a 64-bit int.
- //
+ //
uint64_t srcSize =
target.getTargetData().getTypeSize(leftVal->getType());
Type* tmpTypeToUse =
(srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
- MachineCodeForInstruction &destMCFI =
+ MachineCodeForInstruction &destMCFI =
MachineCodeForInstruction::get(dest);
srcForCast = new TmpInstruction(destMCFI, tmpTypeToUse, dest);
@@ -3395,7 +3395,7 @@
break;
}
// ELSE FALL THROUGH
-
+
case 33: // reg: Add(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseAddInstruction(subtreeRoot), subtreeRoot, mvec);
@@ -3409,7 +3409,7 @@
break;
}
// ELSE FALL THROUGH
-
+
case 34: // reg: Sub(reg, reg)
maskUnsignedResult = true;
Add3OperandInstr(ChooseSubInstructionByType(
@@ -3419,7 +3419,7 @@
case 135: // reg: Mul(todouble, todouble)
checkCast = true;
- // FALL THROUGH
+ // FALL THROUGH
case 35: // reg: Mul(reg, reg)
{
@@ -3437,7 +3437,7 @@
}
case 335: // reg: Mul(todouble, todoubleConst)
checkCast = true;
- // FALL THROUGH
+ // FALL THROUGH
case 235: // reg: Mul(reg, Constant)
{
@@ -3461,7 +3461,7 @@
if (mvec.size() > L)
break;
// ELSE FALL THROUGH
-
+
case 36: // reg: Div(reg, reg)
{
maskUnsignedResult = true;
@@ -3510,12 +3510,12 @@
Value* divOp2 = subtreeRoot->rightChild()->getValue();
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(remI);
-
+
// If second operand of divide is smaller than 64 bits, we have
// to make sure the unused top bits are correct because they affect
// the result. These bits are already correct for unsigned values.
// They may be incorrect for signed values, so sign extend to fill in.
- //
+ //
Value* divOpToUse = divOp2;
if (divOp2->getType()->isSigned()) {
unsigned opSize=target.getTargetData().getTypeSize(divOp2->getType());
@@ -3530,22 +3530,22 @@
// Now compute: result = rem V1, V2 as:
// result = V1 - (V1 / signExtend(V2)) * signExtend(V2)
- //
+ //
TmpInstruction* quot = new TmpInstruction(mcfi, divOp1, divOpToUse);
TmpInstruction* prod = new TmpInstruction(mcfi, quot, divOpToUse);
mvec.push_back(BuildMI(ChooseDivInstruction(target, subtreeRoot), 3)
.addReg(divOp1).addReg(divOpToUse).addRegDef(quot));
-
+
mvec.push_back(BuildMI(ChooseMulInstructionByType(remI->getType()), 3)
.addReg(quot).addReg(divOpToUse).addRegDef(prod));
-
+
mvec.push_back(BuildMI(ChooseSubInstructionByType(remI->getType()), 3)
.addReg(divOp1).addReg(prod).addRegDef(remI));
-
+
break;
}
-
+
case 38: // bool: And(bool, bool)
case 138: // bool: And(bool, not)
case 238: // bool: And(bool, boolconst)
@@ -3638,17 +3638,17 @@
case 41: // setCCconst: SetCC(reg, Constant)
{ // Comparison is with a constant:
- //
+ //
// If the bool result must be computed into a register (see below),
// and the constant is int ZERO, we can use the MOVR[op] instructions
// and avoid the SUBcc instruction entirely.
// Otherwise this is just the same as case 42, so just fall through.
- //
+ //
// The result of the SetCC must be computed and stored in a register if
// it is used outside the current basic block (so it must be computed
// as a boolreg) or it is used by anything other than a branch.
// We will use a conditional move to do this.
- //
+ //
Instruction* setCCInstr = subtreeRoot->getInstruction();
bool computeBoolVal = (subtreeRoot->parent() == NULL ||
! AllUsesAreBranches(setCCInstr));
@@ -3659,7 +3659,7 @@
constNode->getNodeType() ==InstrTreeNode::NTConstNode);
Constant *constVal = cast<Constant>(constNode->getValue());
bool isValidConst;
-
+
if ((constVal->getType()->isInteger()
|| isa<PointerType>(constVal->getType()))
&& ConvertConstantToIntType(target,
@@ -3671,7 +3671,7 @@
// Unconditionally set register to 0
mvec.push_back(BuildMI(V9::SETHI, 2).addZImm(0)
.addRegDef(setCCInstr));
-
+
// Now conditionally move 1 into the register.
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
@@ -3680,7 +3680,7 @@
.addReg(subtreeRoot->leftChild()->getValue())
.addZImm(1)
.addReg(setCCInstr, MachineOperand::UseAndDef));
-
+
break;
}
}
@@ -3691,21 +3691,21 @@
{
// This generates a SUBCC instruction, putting the difference in a
// result reg. if needed, and/or setting a condition code if needed.
- //
+ //
Instruction* setCCInstr = subtreeRoot->getInstruction();
Value* leftVal = subtreeRoot->leftChild()->getValue();
Value* rightVal = subtreeRoot->rightChild()->getValue();
const Type* opType = leftVal->getType();
bool isFPCompare = opType->isFloatingPoint();
-
+
// If the boolean result of the SetCC is used outside the current basic
// block (so it must be computed as a boolreg) or is used by anything
// other than a branch, the boolean must be computed and stored
// in a result register. We will use a conditional move to do this.
- //
+ //
bool computeBoolVal = (subtreeRoot->parent() == NULL ||
! AllUsesAreBranches(setCCInstr));
-
+
// A TmpInstruction is created to represent the CC "result".
// Unlike other instances of TmpInstruction, this one is used
// by machine code of multiple LLVM instructions, viz.,
@@ -3716,7 +3716,7 @@
// condition code. Think of this as casting the bool result to
// a FP condition code register.
// Later, we mark the 4th operand as being a CC register, and as a def.
- //
+ //
TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
setCCInstr->getParent()->getParent(),
leftVal->getType(),
@@ -3725,19 +3725,19 @@
// If the operands are signed values smaller than 4 bytes, then they
// must be sign-extended in order to do a valid 32-bit comparison
// and get the right result in the 32-bit CC register (%icc).
- //
+ //
Value* leftOpToUse = leftVal;
Value* rightOpToUse = rightVal;
if (opType->isIntegral() && opType->isSigned()) {
unsigned opSize = target.getTargetData().getTypeSize(opType);
if (opSize < 4) {
MachineCodeForInstruction& mcfi =
- MachineCodeForInstruction::get(setCCInstr);
+ MachineCodeForInstruction::get(setCCInstr);
// create temporary virtual regs. to hold the sign-extensions
leftOpToUse = new TmpInstruction(mcfi, leftVal);
rightOpToUse = new TmpInstruction(mcfi, rightVal);
-
+
// sign-extend each operand and put the result in the temporary reg.
CreateSignExtensionInstructions
(target, setCCInstr->getParent()->getParent(),
@@ -3763,7 +3763,7 @@
.addReg(leftOpToUse)
.addReg(rightOpToUse));
}
-
+
if (computeBoolVal) {
MachineOpCode movOpCode = (isFPCompare
? ChooseMovFpcciInstruction(subtreeRoot)
@@ -3772,7 +3772,7 @@
// Unconditionally set register to 0
M = BuildMI(V9::SETHI, 2).addZImm(0).addRegDef(setCCInstr);
mvec.push_back(M);
-
+
// Now conditionally move 1 into the register.
// Mark the register as a use (as well as a def) because the old
// value will be retained if the condition is false.
@@ -3781,8 +3781,8 @@
mvec.push_back(M);
}
break;
- }
-
+ }
+
case 51: // reg: Load(reg)
case 52: // reg: Load(ptrreg)
SetOperandsForMemInstr(ChooseLoadInstruction(
@@ -3815,15 +3815,15 @@
AllocationInst* instr =
cast<AllocationInst>(subtreeRoot->getInstruction());
const Type* eltType = instr->getAllocatedType();
-
+
// If #elements is constant, use simpler code for fixed-size allocas
int tsize = (int) target.getTargetData().getTypeSize(eltType);
Value* numElementsVal = NULL;
bool isArray = instr->isArrayAllocation();
-
+
if (!isArray || isa<Constant>(numElementsVal = instr->getArraySize())) {
// total size is constant: generate code for fixed-size alloca
- unsigned numElements = isArray?
+ unsigned numElements = isArray?
cast<ConstantUInt>(numElementsVal)->getValue() : 1;
CreateCodeForFixedSizeAlloca(target, instr, tsize,
numElements, mvec);
@@ -3841,18 +3841,18 @@
// register (for indirect calls), the operands of the Call,
// and the return value (if any) as implicit operands
// of the machine instruction.
- //
+ //
// If this is a varargs function, floating point arguments
// have to passed in integer registers so insert
// copy-float-to-int instructions for each float operand.
- //
+ //
CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
Value *callee = callInstr->getCalledValue();
Function* calledFunc = dyn_cast<Function>(callee);
// Check if this is an intrinsic function that needs a special code
// sequence (e.g., va_start). Indirect calls cannot be special.
- //
+ //
bool specialIntrinsic = false;
Intrinsic::ID iid;
if (calledFunc && (iid=(Intrinsic::ID)calledFunc->getIntrinsicID()))
@@ -3860,12 +3860,12 @@
// If not, generate the normal call sequence for the function.
// This can also handle any intrinsics that are just function calls.
- //
+ //
if (! specialIntrinsic) {
Function* currentFunc = callInstr->getParent()->getParent();
MachineFunction& MF = MachineFunction::get(currentFunc);
MachineCodeForInstruction& mcfi =
- MachineCodeForInstruction::get(callInstr);
+ MachineCodeForInstruction::get(callInstr);
const SparcV9RegInfo& regInfo =
(SparcV9RegInfo&) *target.getRegInfo();
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
@@ -3879,7 +3879,7 @@
// the PC-relative address fits in the CALL address field (22 bits).
// Use JMPL for indirect calls.
// This will be added to mvec later, after operand copies.
- //
+ //
MachineInstr* callMI;
if (calledFunc) // direct function call
callMI = BuildMI(V9::CALL, 1).addPCDisp(callee);
@@ -3892,7 +3892,7 @@
->getElementType());
bool isVarArgs = funcType->isVarArg();
bool noPrototype = isVarArgs && funcType->getNumParams() == 0;
-
+
// Use a descriptor to pass information about call arguments
// to the register allocator. This descriptor will be "owned"
// and freed automatically when the MachineCodeForInstruction
@@ -3905,7 +3905,7 @@
// Insert sign-extension instructions for small signed values,
// if this is an unknown function (i.e., called via a funcptr)
// or an external one (i.e., which may not be compiled by llc).
- //
+ //
if (calledFunc == NULL || calledFunc->isExternal()) {
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
Value* argVal = callInstr->getOperand(i);
@@ -3930,7 +3930,7 @@
// Insert copy instructions to get all the arguments into
// all the places that they need to be.
- //
+ //
for (unsigned i=1, N=callInstr->getNumOperands(); i < N; ++i) {
int argNo = i-1;
CallArgInfo& argInfo = argDesc->getArgInfo(argNo);
@@ -3955,7 +3955,7 @@
// may go in a register or on the stack. The copy instruction
// to the outgoing reg/stack is created by the normal argument
// handling code since this is the "normal" passing mode.
- //
+ //
regNumForArg = regInfo.regNumForFPArg(regType,
false, false, argNo,
regClassIDOfArgReg);
@@ -3964,7 +3964,7 @@
else
argInfo.setUseFPArgReg();
}
-
+
// If this arg. is in the first $K$ regs, add special copy-
// float-to-int instructions to pass the value as an int.
// To check if it is in the first $K$, get the register
@@ -3972,7 +3972,7 @@
// generated here because they are extra cases and not needed
// for the normal argument handling (some code reuse is
// possible though -- later).
- //
+ //
int copyRegNum = regInfo.regNumForIntArg(false, false, argNo,
regClassIDOfArgReg);
if (copyRegNum != regInfo.getInvalidRegNum()) {
@@ -3984,25 +3984,25 @@
argVal, NULL,
"argRegCopy");
callMI->addImplicitRef(argVReg);
-
+
// Get a temp stack location to use to copy
// float-to-int via the stack.
- //
+ //
// FIXME: For now, we allocate permanent space because
// the stack frame manager does not allow locals to be
// allocated (e.g., for alloca) after a temp is
// allocated!
- //
+ //
// int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->pushTempValue(argSize);
int tmpOffset = MF.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(argVReg);
-
+
// Generate the store from FP reg to stack
unsigned StoreOpcode = ChooseStoreInstruction(argType);
M = BuildMI(convertOpcodeFromRegToImm(StoreOpcode), 3)
.addReg(argVal).addMReg(regInfo.getFramePointer())
.addSImm(tmpOffset);
mvec.push_back(M);
-
+
// Generate the load from stack to int arg reg
unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
M = BuildMI(convertOpcodeFromRegToImm(LoadOpcode), 3)
@@ -4045,11 +4045,11 @@
regNumForArg =regInfo.getUnifiedRegNum(regClassIDOfArgReg,
regNumForArg);
}
- }
+ }
- //
+ //
// Now insert copy instructions to stack slot or arg. register
- //
+ //
if (argInfo.usesStackSlot()) {
// Get the stack offset for this argument slot.
// FP args on stack are right justified so adjust offset!
@@ -4076,11 +4076,11 @@
// Create a virtual register to represent the arg reg. Mark
// this vreg as being an implicit operand of the call MI.
- TmpInstruction* argVReg =
+ TmpInstruction* argVReg =
new TmpInstruction(mcfi, argVal, NULL, "argReg");
callMI->addImplicitRef(argVReg);
-
+
// Generate the reg-to-reg copy into the outgoing arg reg.
// -- For FP values, create a FMOVS or FMOVD instruction
// -- For non-FP values, create an add-with-0 instruction
@@ -4091,7 +4091,7 @@
M = (BuildMI(ChooseAddInstructionByType(argType), 3)
.addReg(argVal).addSImm((int64_t) 0)
.addReg(argVReg, MachineOperand::Def));
-
+
// Mark the operand with the register it should be assigned
M->SetRegForOperand(M->getNumOperands()-1, regNumForArg);
callMI->SetRegForImplicitRef(callMI->getNumImplicitRefs()-1,
@@ -4111,20 +4111,20 @@
// Add the return value as an implicit ref. The call operands
// were added above. Also, add code to copy out the return value.
// This is always register-to-register for int or FP return values.
- //
- if (callInstr->getType() != Type::VoidTy) {
+ //
+ if (callInstr->getType() != Type::VoidTy) {
// Get the return value reg.
const Type* retType = callInstr->getType();
int regNum = (retType->isFloatingPoint()
- ? (unsigned) SparcV9FloatRegClass::f0
+ ? (unsigned) SparcV9FloatRegClass::f0
: (unsigned) SparcV9IntRegClass::o0);
unsigned regClassID = regInfo.getRegClassIDOfType(retType);
regNum = regInfo.getUnifiedRegNum(regClassID, regNum);
// Create a virtual register to represent it and mark
// this vreg as being an implicit operand of the call MI
- TmpInstruction* retVReg =
+ TmpInstruction* retVReg =
new TmpInstruction(mcfi, callInstr, NULL, "argReg");
callMI->addImplicitRef(retVReg, /*isDef*/ true);
@@ -4157,27 +4157,27 @@
break;
}
-
+
case 62: // reg: Shl(reg, reg)
{
Value* argVal1 = subtreeRoot->leftChild()->getValue();
Value* argVal2 = subtreeRoot->rightChild()->getValue();
Instruction* shlInstr = subtreeRoot->getInstruction();
-
+
const Type* opType = argVal1->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
"Shl unsupported for other types");
unsigned opSize = target.getTargetData().getTypeSize(opType);
-
+
CreateShiftInstructions(target, shlInstr->getParent()->getParent(),
(opSize > 4)? V9::SLLXr6:V9::SLLr5,
argVal1, argVal2, 0, shlInstr, mvec,
MachineCodeForInstruction::get(shlInstr));
break;
}
-
+
case 63: // reg: Shr(reg, reg)
- {
+ {
const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
assert((opType->isInteger() || isa<PointerType>(opType)) &&
"Shr unsupported for other types");
@@ -4188,7 +4188,7 @@
subtreeRoot, mvec);
break;
}
-
+
case 64: // reg: Phi(reg,reg)
break; // don't forward the value
@@ -4216,7 +4216,7 @@
addSImm(0).addRegDef(vaArgI));
break;
}
-
+
case 71: // reg: VReg
case 72: // reg: Constant
break; // don't forward the value
@@ -4256,12 +4256,12 @@
unsigned destSize=target.getTargetData().getTypeSize(dest->getType());
if (destSize <= 4) {
// Mask high 64 - N bits, where N = 4*destSize.
-
+
// Use a TmpInstruction to represent the
// intermediate result before masking. Since those instructions
// have already been generated, go back and substitute tmpI
// for dest in the result position of each one of them.
- //
+ //
MachineCodeForInstruction& mcfi = MachineCodeForInstruction::get(dest);
TmpInstruction *tmpI = new TmpInstruction(mcfi, dest->getType(),
dest, NULL, "maskHi");
@@ -4278,7 +4278,7 @@
// introduce a use of `tmpI' with no preceding def. Therefore,
// substitute a use or def-and-use operand only if a previous def
// operand has already been substituted (i.e., numSubst > 0).
- //
+ //
numSubst += mvec[i]->substituteValue(dest, tmpI,
/*defsOnly*/ numSubst == 0,
/*notDefsAndUses*/ numSubst > 0,
@@ -4354,13 +4354,13 @@
<< F.getName() << "\n\n";
instrForest.dump();
}
-
+
// Invoke BURG instruction selection for each tree
for (InstrForest::const_root_iterator RI = instrForest.roots_begin();
RI != instrForest.roots_end(); ++RI) {
InstructionNode* basicNode = *RI;
- assert(basicNode->parent() == NULL && "A `root' node has a parent?");
-
+ assert(basicNode->parent() == NULL && "A `root' node has a parent?");
+
// Invoke BURM to label each tree node with a state
burm_label(basicNode);
if (SelectDebugLevel >= Select_DebugBurgTrees) {
@@ -4368,11 +4368,11 @@
std::cerr << "\nCover cost == " << treecost(basicNode, 1, 0) <<"\n\n";
printMatches(basicNode);
}
-
+
// Then recursively walk the tree to select instructions
SelectInstructionsForTree(basicNode, /*goalnt*/1);
}
-
+
// Create the MachineBasicBlocks and add all of the MachineInstrs
// defined in the MachineCodeForInstruction objects to the MachineBasicBlocks.
MachineFunction &MF = MachineFunction::get(&F);
@@ -4403,12 +4403,12 @@
// Insert phi elimination code
InsertCodeForPhis(F);
-
+
if (SelectDebugLevel >= Select_PrintMachineCode) {
std::cerr << "\n*** Machine instructions after INSTRUCTION SELECTION\n";
MachineFunction::get(&F).dump();
}
-
+
return true;
}
@@ -4434,7 +4434,7 @@
MachineCodeForInstruction &MCforPN = MachineCodeForInstruction::get (PN);
for (unsigned i = 0; i < PN->getNumIncomingValues(); ++i) {
std::vector<MachineInstr*> mvec, CpVec;
- Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
+ Target.getRegInfo()->cpValue2Value(PN->getIncomingValue(i),
PhiCpRes, mvec);
for (std::vector<MachineInstr*>::iterator MI=mvec.begin();
MI != mvec.end(); ++MI) {
@@ -4443,7 +4443,7 @@
CpVec2.push_back(*MI);
CpVec.insert(CpVec.end(), CpVec2.begin(), CpVec2.end());
}
- // Insert the copy instructions into the predecessor BB.
+ // Insert the copy instructions into the predecessor BB.
InsertPhiElimInstructions(PN->getIncomingBlock(i), CpVec);
MCforPN.insert (MCforPN.end (), CpVec.begin (), CpVec.end ());
}
@@ -4463,7 +4463,7 @@
///
void V9ISel::InsertPhiElimInstructions(BasicBlock *BB,
const std::vector<MachineInstr*>& CpVec)
-{
+{
Instruction *TermInst = (Instruction*)BB->getTerminator();
MachineCodeForInstruction &MC4Term = MachineCodeForInstruction::get(TermInst);
MachineInstr *FirstMIOfTerm = MC4Term.front();
@@ -4473,7 +4473,7 @@
assert(MBB && "Machine BB for predecessor's terminator not found");
MachineBasicBlock::iterator MCIt = FirstMIOfTerm;
assert(MCIt != MBB->end() && "Start inst of terminator not found");
-
+
// Insert the copy instructions just before the first machine instruction
// generated for the terminator.
MBB->insert(MCIt, CpVec.begin(), CpVec.end());
@@ -4482,7 +4482,7 @@
/// SelectInstructionsForTree - Recursively walk the tree to select
/// instructions. Do this top-down so that child instructions can exploit
/// decisions made at the child instructions.
-///
+///
/// E.g., if br(setle(reg,const)) decides the constant is 0 and uses
/// a branch-on-integer-register instruction, then the setle node
/// can use that information to avoid generating the SUBcc instruction.
@@ -4494,15 +4494,15 @@
void V9ISel::SelectInstructionsForTree(InstrTreeNode* treeRoot, int goalnt) {
// Get the rule that matches this node.
int ruleForNode = burm_rule(treeRoot->state, goalnt);
-
+
if (ruleForNode == 0) {
std::cerr << "Could not match instruction tree for instr selection\n";
abort();
}
-
+
// Get this rule's non-terminals and the corresponding child nodes (if any)
short *nts = burm_nts[ruleForNode];
-
+
// First, select instructions for the current node and rule.
// (If this is a list node, not an instruction, then skip this step).
// This function is specific to the target architecture.
@@ -4511,19 +4511,19 @@
InstructionNode* instrNode = (InstructionNode*)treeRoot;
assert(instrNode->getNodeType() == InstrTreeNode::NTInstructionNode);
GetInstructionsByRule(instrNode, ruleForNode, nts, Target, minstrVec);
- MachineCodeForInstruction &mvec =
+ MachineCodeForInstruction &mvec =
MachineCodeForInstruction::get(instrNode->getInstruction());
mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
}
-
+
// Then, recursively compile the child nodes, if any.
- //
+ //
if (nts[0]) {
// i.e., there is at least one kid
InstrTreeNode* kids[2];
int currentRule = ruleForNode;
burm_kids(treeRoot, currentRule, kids);
-
+
// First skip over any chain rules so that we don't visit
// the current node again.
while (ThisIsAChainRule(currentRule)) {
@@ -4531,7 +4531,7 @@
nts = burm_nts[currentRule];
burm_kids(treeRoot, currentRule, kids);
}
-
+
// Now we have the first non-chain rule so we have found
// the actual child nodes. Recursively compile them.
for (unsigned i = 0; nts[i]; i++) {
@@ -4542,7 +4542,7 @@
SelectInstructionsForTree(kids[i], nts[i]);
}
}
-
+
// Finally, do any post-processing on this node after its children
// have been translated.
if (treeRoot->opLabel != VRegListOp)
Index: llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.79 llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.80
--- llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp:1.79 Thu Dec 16 10:47:56 2004
+++ llvm/lib/Target/SparcV9/SparcV9CodeEmitter.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9CodeEmitter.cpp --------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// SPARC-specific backend for emitting machine code to memory.
@@ -52,7 +52,7 @@
MCE.emitWord(Val);
}
-unsigned
+unsigned
SparcV9CodeEmitter::getRealRegNum(unsigned fakeReg,
MachineInstr &MI) {
const SparcV9RegInfo &RI = *TM.getRegInfo();
@@ -70,12 +70,12 @@
16, 17, 18, 19, 20, 21, 22, 23,
// "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
24, 25, 26, 27, 28, 29, 30, 31,
- // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ // "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
0, 1, 2, 3, 4, 5, 6, 7,
// "o6"
14
- };
-
+ };
+
return IntRegMap[fakeReg];
break;
}
@@ -90,16 +90,16 @@
// The bit layout becomes: b[4], b[3], b[2], b[1], b[5]
fakeReg |= (fakeReg >> 5) & 1;
fakeReg &= 0x1f;
- DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
+ DEBUG(std::cerr << "FP double reg, returning: " << fakeReg << "\n");
}
return fakeReg;
}
case SparcV9RegInfo::IntCCRegClassID: {
/* xcc, icc, ccr */
static const unsigned IntCCReg[] = { 6, 4, 2 };
-
+
assert(fakeReg < sizeof(IntCCReg)/sizeof(IntCCReg[0])
- && "CC register out of bounds for IntCCReg map");
+ && "CC register out of bounds for IntCCReg map");
DEBUG(std::cerr << "IntCC reg: " << IntCCReg[fakeReg] << "\n");
return IntCCReg[fakeReg];
}
@@ -113,7 +113,7 @@
// instructions and 0 in SparcV9SpecialRegClass.
static const unsigned SpecialReg[] = { 1 };
assert(fakeReg < sizeof(SpecialReg)/sizeof(SpecialReg[0])
- && "Special register out of bounds for SpecialReg map");
+ && "Special register out of bounds for SpecialReg map");
DEBUG(std::cerr << "Special reg: " << SpecialReg[fakeReg] << "\n");
return SpecialReg[fakeReg];
}
@@ -176,14 +176,14 @@
unsigned fakeReg = MO.getReg();
unsigned realRegByClass = getRealRegNum(fakeReg, MI);
DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
- << realRegByClass << " (LLC: "
+ << realRegByClass << " (LLC: "
<< TM.getRegInfo()->getUnifiedRegName(fakeReg) << ")\n");
rv = realRegByClass;
} else if (MO.isImmediate()) {
rv = MO.getImmedValue();
DEBUG(std::cerr << "immed: " << rv << "\n");
} else if (MO.isMachineBasicBlock()) {
- // Duplicate code of the above case for VirtualRegister, BasicBlock...
+ // Duplicate code of the above case for VirtualRegister, BasicBlock...
// It should really hit this case, but SparcV9 backend uses VRegs instead
DEBUG(std::cerr << "Saving reference to MBB\n");
const BasicBlock *BB = MO.getMachineBasicBlock()->getBasicBlock();
@@ -231,7 +231,7 @@
bool SparcV9CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
MCE.startFunction(MF);
DEBUG(std::cerr << "Starting function " << MF.getFunction()->getName()
- << ", address: " << "0x" << std::hex
+ << ", address: " << "0x" << std::hex
<< (long)MCE.getCurrentPCValue() << "\n");
MCE.emitConstantPool(MF.getConstantPool());
@@ -257,7 +257,7 @@
// Ref is the location of the instruction, and hence the PC
int64_t branchTarget = (Location - (long)Ref) >> 2;
// Save the flags.
- bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
+ bool loBits32=false, hiBits32=false, loBits64=false, hiBits64=false;
if (op.isLoBits32()) { loBits32=true; }
if (op.isHiBits32()) { hiBits32=true; }
if (op.isLoBits64()) { loBits64=true; }
Index: llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.7 llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.8
--- llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp:1.7 Wed Aug 18 13:13:34 2004
+++ llvm/lib/Target/SparcV9/SparcV9FrameInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,14 +1,14 @@
//===-- SparcV9FrameInfo.cpp - Stack frame layout info for SparcV9 --------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Interface to stack frame layout info for the UltraSPARC.
-//
+//
//===----------------------------------------------------------------------===//
#include "llvm/CodeGen/MachineFunction.h"
@@ -19,21 +19,21 @@
using namespace llvm;
int
-SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
+SparcV9FrameInfo::getRegSpillAreaOffset(MachineFunction& mcInfo, bool& pos) const
{
// ensure no more auto vars are added
mcInfo.getInfo<SparcV9FunctionInfo>()->freezeAutomaticVarsArea();
-
+
pos = false; // static stack area grows downwards
unsigned autoVarsSize = mcInfo.getInfo<SparcV9FunctionInfo>()->getAutomaticVarsSize();
- return StaticAreaOffsetFromFP - autoVarsSize;
+ return StaticAreaOffsetFromFP - autoVarsSize;
}
int SparcV9FrameInfo::getTmpAreaOffset(MachineFunction& mcInfo, bool& pos) const {
SparcV9FunctionInfo *MFI = mcInfo.getInfo<SparcV9FunctionInfo>();
MFI->freezeAutomaticVarsArea(); // ensure no more auto vars are added
MFI->freezeSpillsArea(); // ensure no more spill slots are added
-
+
pos = false; // static stack area grows downwards
unsigned autoVarsSize = MFI->getAutomaticVarsSize();
unsigned spillAreaSize = MFI->getRegSpillsSize();
Index: llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.1 llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.2
--- llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp:1.1 Mon Nov 22 14:24:27 2004
+++ llvm/lib/Target/SparcV9/SparcV9JITInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcJITInfo.cpp - Implement the JIT interfaces for SparcV9 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the SparcV9 target.
@@ -57,7 +57,7 @@
Addr[4] = 0x82114001;
// or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
Addr[5] = BUILD_ORI(G1, JumpTarget, G1);
-
+
// jmpl %g1, %g0, %g0 ;; indirect branch on %g1
Addr[6] = 0x81C00001;
// nop ;; delay slot
@@ -70,13 +70,13 @@
}
-static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
+static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Save condition-code registers
- "stx %%fsr, %0;\n\t"
- "rd %%fprs, %1;\n\t"
+ "stx %%fsr, %0;\n\t"
+ "rd %%fprs, %1;\n\t"
"rd %%ccr, %2;\n\t"
: "=m"(CC[0]), "=r"(CC[1]), "=r"(CC[2]));
@@ -103,7 +103,7 @@
"=m"(DoubleFP[10]), "=m"(DoubleFP[11]),
"=m"(DoubleFP[12]), "=m"(DoubleFP[13]),
"=m"(DoubleFP[14]), "=m"(DoubleFP[15]));
-
+
__asm__ __volatile__ (// Save Double FP registers, part 2
"std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
"std %%f36, %2;\n\t" "std %%f38, %3;\n\t"
@@ -127,14 +127,14 @@
#endif
}
-static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
+static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Restore condition-code registers
- "ldx %0, %%fsr;\n\t"
+ "ldx %0, %%fsr;\n\t"
"wr %1, 0, %%fprs;\n\t"
- "wr %2, 0, %%ccr;\n\t"
+ "wr %2, 0, %%ccr;\n\t"
:: "m"(CC[0]), "r"(CC[1]), "r"(CC[2]));
__asm__ __volatile__ (// Restore globals g1 and g5
@@ -144,11 +144,11 @@
// GCC says: `asm' only allows up to thirty parameters!
__asm__ __volatile__ (// Restore Single/Double FP registers, part 1
- "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
- "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
- "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
- "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
- "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
+ "ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
+ "ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
+ "ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
+ "ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
+ "ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
"ldd %10, %%f20;\n\t" "ldd %11, %%f22;\n\t"
"ldd %12, %%f24;\n\t" "ldd %13, %%f26;\n\t"
"ldd %14, %%f28;\n\t" "ldd %15, %%f30;\n\t"
@@ -228,7 +228,7 @@
// has been performed. Having a variable sized alloca disables frame pointer
// elimination currently, even if it's dead. This is a gross hack.
alloca(42+Offset);
-
+
// Make sure that what we're about to overwrite is indeed "save".
if (*CodeBegin != 0x9DE3BF40) {
std::cerr << "About to overwrite smthg not a save instr!";
@@ -264,7 +264,7 @@
///
void *SparcV9JITInfo::emitFunctionStub(void *Fn, MachineCodeEmitter &MCE) {
if (Fn != CompilationCallback) {
- // If this is just a call to an external function,
+ // If this is just a call to an external function,
MCE.startFunctionStub(4*8);
unsigned *Stub = (unsigned*)(intptr_t)MCE.getCurrentPCValue();
for (unsigned i = 0; i != 8; ++i)
Index: llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.26 llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.27
--- llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp:1.26 Wed Sep 1 17:55:36 2004
+++ llvm/lib/Target/SparcV9/SparcV9PeepholeOpts.cpp Thu Apr 21 18:25:42 2005
@@ -1,12 +1,12 @@
//===-- SparcV9PeepholeOpts.cpp -------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Support for performing several peephole opts in one or a few passes over the
// machine code of a method.
//
@@ -37,13 +37,13 @@
// This instruction is in a delay slot of its predecessor, so
// replace it with a nop. By replacing in place, we save having
// to update the I-I maps.
- //
+ //
assert(ndelay == 1 && "Not yet handling multiple-delay-slot targets");
BBI->replace(V9::NOP, 0);
return;
}
}
-
+
// The instruction is not in a delay slot, so we can simply erase it.
mvec.erase(BBI);
BBI = mvec.end();
@@ -68,13 +68,13 @@
} else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
unsigned srcWithDestReg;
-
+
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
MI->getOperand(srcWithDestReg).getReg()
== MI->getOperand(2).getReg())
break;
-
+
if (srcWithDestReg == 2)
return false;
else {
@@ -84,7 +84,7 @@
(MI->getOperand(otherOp).hasAllocatedReg() &&
MI->getOperand(otherOp).getReg() ==
target.getRegInfo()->getZeroRegNum()) ||
-
+
// or operand otherOp == 0
(MI->getOperand(otherOp).getType()
== MachineOperand::MO_SignExtendedImmed &&
@@ -126,7 +126,7 @@
// Apply a list of peephole optimizations to this machine instruction
// within its local context. They are allowed to delete MI or any
-// instruction before MI, but not
+// instruction before MI, but not
//
bool PeepholeOpts::visit(MachineBasicBlock& mvec,
MachineBasicBlock::iterator BBI) const {
Index: llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.42 llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.43
--- llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp:1.42 Fri Jan 28 18:36:38 2005
+++ llvm/lib/Target/SparcV9/SparcV9PreSelection.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9PreSelection.cpp - Specialize LLVM code for SparcV9 ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the PreSelection pass which specializes LLVM code for
@@ -34,7 +34,7 @@
//===--------------------------------------------------------------------===//
// PreSelection Pass - Specialize LLVM code for the SparcV9 instr. selector.
- //
+ //
class PreSelection : public FunctionPass, public InstVisitor<PreSelection> {
const TargetInstrInfo &instrInfo;
@@ -50,7 +50,7 @@
const char *getPassName() const { return "SparcV9 Instr. Pre-selection"; }
// These methods do the actual work of specializing code
- void visitInstruction(Instruction &I); // common work for every instr.
+ void visitInstruction(Instruction &I); // common work for every instr.
void visitGetElementPtrInst(GetElementPtrInst &I);
void visitCallInst(CallInst &I);
void visitPHINode(PHINode &PN);
@@ -65,12 +65,12 @@
}
// Helper functions for visiting operands of every instruction
- //
+ //
// visitOperands() works on every operand in [firstOp, lastOp-1].
// If lastOp==0, lastOp defaults to #operands or #incoming Phi values.
- //
+ //
// visitOneOperand() does all the work for one operand.
- //
+ //
void visitOperands(Instruction &I, int firstOp=0);
void visitOneOperand(Instruction &I, Value* Op, unsigned opNum,
Instruction& insertBefore);
@@ -110,7 +110,7 @@
Instruction& insertBefore)
{
Value *getArg1, *getArg2;
-
+
switch(CE->getOpcode())
{
case Instruction::Cast:
@@ -131,7 +131,7 @@
return new GetElementPtrInst(getArg1,
std::vector<Value*>(CE->op_begin()+1, CE->op_end()),
"constantGEP:" + getArg1->getName(), &insertBefore);
-
+
case Instruction::Select: {
Value *C, *S1, *S2;
C = CE->getOperand (0);
@@ -145,7 +145,7 @@
S2 = DecomposeConstantExpr (CEarg, insertBefore);
return new SelectInst (C, S1, S2, "constantSelect", &insertBefore);
}
-
+
default: // must be a binary operator
assert(CE->getOpcode() >= Instruction::BinaryOpsBegin &&
CE->getOpcode() < Instruction::BinaryOpsEnd &&
@@ -206,10 +206,10 @@
/// depends on the type of instruction and on the target architecture.
/// -- For any constants that cannot be put in an immediate field,
/// load address into virtual register first, and then load the constant.
-///
+///
/// firstOp and lastOp can be used to skip leading and trailing operands.
/// If lastOp is 0, it defaults to #operands or #incoming Phi values.
-///
+///
inline void PreSelection::visitOperands(Instruction &I, int firstOp) {
// For any instruction other than PHI, copies go just before the instr.
for (unsigned i = firstOp, e = I.getNumOperands(); i != e; ++i)
@@ -221,7 +221,7 @@
// For a PHI, operand copies must be before the terminator of the
// appropriate predecessor basic block. Remaining logic is simple
// so just handle PHIs and other instructions separately.
- //
+ //
for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i)
visitOneOperand(PN, PN.getIncomingValue(i),
PN.getOperandNumForIncomingValue(i),
@@ -231,12 +231,12 @@
// Common work for *all* instructions. This needs to be called explicitly
// by other visit<InstructionType> functions.
-inline void PreSelection::visitInstruction(Instruction &I) {
+inline void PreSelection::visitInstruction(Instruction &I) {
visitOperands(I); // Perform operand transformations
}
// GetElementPtr instructions: check if pointer is a global
-void PreSelection::visitGetElementPtrInst(GetElementPtrInst &I) {
+void PreSelection::visitGetElementPtrInst(GetElementPtrInst &I) {
Instruction* curI = &I;
// The Sparc backend doesn't handle array indexes that are not long types, so
Index: llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.47 llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.48
--- llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp:1.47 Wed Aug 18 13:13:34 2004
+++ llvm/lib/Target/SparcV9/SparcV9PrologEpilogInserter.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9PrologEpilogCodeInserter.cpp - Insert Fn Prolog & Epilog ---===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This is the SparcV9 target's own PrologEpilogInserter. It creates prolog and
@@ -34,7 +34,7 @@
namespace {
struct InsertPrologEpilogCode : public MachineFunctionPass {
const char *getPassName() const { return "SparcV9 Prolog/Epilog Inserter"; }
-
+
bool runOnMachineFunction(MachineFunction &F) {
if (!F.getInfo<SparcV9FunctionInfo>()->isCompiledAsLeafMethod()) {
InsertPrologCode(F);
@@ -42,7 +42,7 @@
}
return false;
}
-
+
void InsertPrologCode(MachineFunction &F);
void InsertEpilogCode(MachineFunction &F);
};
@@ -54,7 +54,7 @@
unsigned staticStackSize = MF.getInfo<SparcV9FunctionInfo>()->getStaticStackSize();
if (staticStackSize < (unsigned)SparcV9FrameInfo::MinStackFrameSize)
staticStackSize = SparcV9FrameInfo::MinStackFrameSize;
- if (unsigned padsz = staticStackSize %
+ if (unsigned padsz = staticStackSize %
SparcV9FrameInfo::StackFrameSizeAlignment)
staticStackSize += SparcV9FrameInfo::StackFrameSizeAlignment - padsz;
return staticStackSize;
@@ -65,7 +65,7 @@
std::vector<MachineInstr*> mvec;
const TargetMachine &TM = MF.getTarget();
const TargetFrameInfo& frameInfo = *TM.getFrameInfo();
-
+
// The second operand is the stack size. If it does not fit in the
// immediate field, we have to use a free register to hold the size.
// See the comments below for the choice of this register.
@@ -89,16 +89,16 @@
.addMReg(uregNum, MachineOperand::Def);
M->getOperand(0).markHi32();
mvec.push_back(M);
-
+
M = BuildMI(V9::ORi, 3).addMReg(uregNum).addSImm(C)
.addMReg(uregNum, MachineOperand::Def);
M->getOperand(1).markLo32();
mvec.push_back(M);
-
+
M = BuildMI(V9::SRAi5, 3).addMReg(uregNum).addZImm(0)
.addMReg(uregNum, MachineOperand::Def);
mvec.push_back(M);
-
+
// Now generate the SAVE using the value in register %g1
M = BuildMI(V9::SAVEr,3).addMReg(SP).addMReg(uregNum)
.addMReg(SP,MachineOperand::Def);
@@ -110,7 +110,7 @@
// The first K=6 arguments are always received via int arg regs
// (%i0 ... %i5 if K=6) .
// By copying the varargs arguments to the stack, va_arg() then can
- // simply assume that all vararg arguments are in an array on the stack.
+ // simply assume that all vararg arguments are in an array on the stack.
if (MF.getFunction()->getFunctionType()->isVarArg()) {
int numFixedArgs = MF.getFunction()->getFunctionType()->getNumParams();
int numArgRegs = TM.getRegInfo()->getNumOfIntArgRegs();
@@ -147,13 +147,13 @@
if (TermInst->getOpcode() == Instruction::Ret)
{
int ZR = TM.getRegInfo()->getZeroRegNum();
- MachineInstr *Restore =
+ MachineInstr *Restore =
BuildMI(V9::RESTOREi, 3).addMReg(ZR).addSImm(0)
.addMReg(ZR, MachineOperand::Def);
-
+
MachineCodeForInstruction &termMvec =
MachineCodeForInstruction::get(TermInst);
-
+
// Remove the NOPs in the delay slots of the return instruction
unsigned numNOPs = 0;
while (termMvec.back()->getOpcode() == V9::NOP)
@@ -164,13 +164,13 @@
++numNOPs;
}
assert(termMvec.back() == &MBB.back());
-
+
// Check that we found the right number of NOPs and have the right
// number of instructions to replace them.
unsigned ndelays = MII.getNumDelaySlots(termMvec.back()->getOpcode());
assert(numNOPs == ndelays && "Missing NOPs in delay slots?");
assert(ndelays == 1 && "Cannot use epilog code for delay slots?");
-
+
// Append the epilog code to the end of the basic block.
MBB.push_back(Restore);
}
Index: llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.39 llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.40
--- llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp:1.39 Thu Jul 29 01:43:08 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegClassInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9RegClassInfo.cpp - Register class def'ns for SparcV9 -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines the methods used by the SparcV9 register allocator
@@ -34,7 +34,7 @@
// If there is call interf, try to allocate non-volatile. If that fails
// try to allocate a volatile and insert save across calls
// If both above fail, spill.
-//
+//
//-----------------------------------------------------------------------------
void SparcV9IntRegClass::colorIGNode(IGNode * Node,
const std::vector<bool> &IsColorUsedArr) const
@@ -43,7 +43,7 @@
if (DEBUG_RA)
std::cerr << "\nColoring LR [CallInt=" << LR->isCallInterference() <<"]:"
- << *LR << "\n";
+ << *LR << "\n";
if (LR->hasSuggestedColor()) {
unsigned SugCol = LR->getSuggestedColor();
@@ -69,18 +69,18 @@
bool ColorFound= false; // have we found a color yet?
//if this Node is between calls
- if (! LR->isCallInterference()) {
+ if (! LR->isCallInterference()) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcV9IntRegClass::StartOfAllRegs;
- } else {
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
+ } else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9IntRegClass::StartOfNonVolatileRegs;
}
unsigned c=0; // color
-
+
// find first unused color
- for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
+ for (c=SearchStart; c < SparcV9IntRegClass::NumOfAvailRegs; c++) {
if (!IsColorUsedArr[c]) {
ColorFound = true;
break;
@@ -97,20 +97,20 @@
//
else if (LR->isCallInterference()) {
// start from 0 - try to find even a volatile this time
- SearchStart = SparcV9IntRegClass::StartOfAllRegs;
+ SearchStart = SparcV9IntRegClass::StartOfAllRegs;
// find first unused volatile color
- for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
+ for(c=SearchStart; c < SparcV9IntRegClass::StartOfNonVolatileRegs; c++) {
if (! IsColorUsedArr[c]) {
ColorFound = true;
break;
}
}
- if (ColorFound) {
- LR->setColor(c);
+ if (ColorFound) {
+ LR->setColor(c);
// get the live range corresponding to live var
- // since LR span across calls, must save across calls
+ // since LR span across calls, must save across calls
//
if (DEBUG_RA)
std::cerr << "\n Colored after SECOND search with col " << c;
@@ -121,7 +121,7 @@
// If we couldn't find a color regardless of call interference - i.e., we
// don't have either a volatile or non-volatile color left
//
- if (!ColorFound)
+ if (!ColorFound)
LR->markForSpill(); // no color found - must spill
}
@@ -137,7 +137,7 @@
// if (the LR is a 64-bit comparison) use %xcc
// else /*32-bit or smaller*/ use %icc
// }
-//
+//
// Note: The third name (%ccr) is essentially an assembly mnemonic and
// depends solely on the opcode, so the name can be chosen in EmitAssembly.
//-----------------------------------------------------------------------------
@@ -151,7 +151,7 @@
// because there is only one possible register, but more importantly, the
// spill algorithm cannot find it. In particular, we have to choose
// whether to use %xcc or %icc based on type of value compared
- //
+ //
const LiveRange* ccLR = Node->getParentLR();
const Type* setCCType = (* ccLR->begin())->getType(); // any Value in LR
assert(setCCType->isIntegral() || isa<PointerType>(setCCType));
@@ -178,10 +178,10 @@
const std::vector<bool> &IsColorUsedArr) const {
for(unsigned c = 0; c != 4; ++c)
if (!IsColorUsedArr[c]) { // find unused color
- Node->setColor(c);
+ Node->setColor(c);
return;
}
-
+
Node->getParentLR()->markForSpill();
}
@@ -209,30 +209,30 @@
#ifndef NDEBUG
// Check that the correct colors have been are marked for fp-doubles.
- //
+ //
// FIXME: This is old code that is no longer needed. Temporarily converting
// it into a big assertion just to check that the replacement logic
// (invoking SparcV9FloatRegClass::markColorsUsed() directly from
// RegClass::colorIGNode) works correctly.
- //
+ //
// In fact, this entire function should be identical to
// SparcV9IntRegClass::colorIGNode(), and perhaps can be
- // made into a general case in CodeGen/RegAlloc/RegClass.cpp.
- //
+ // made into a general case in CodeGen/RegAlloc/RegClass.cpp.
+ //
unsigned NumNeighbors = Node->getNumOfNeighbors(); // total # of neighbors
- for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
+ for(unsigned n=0; n < NumNeighbors; n++) { // for each neigh
IGNode *NeighIGNode = Node->getAdjIGNode(n);
LiveRange *NeighLR = NeighIGNode->getParentLR();
-
+
if (NeighLR->hasColor()) {
assert(IsColorUsedArr[ NeighLR->getColor() ]);
if (NeighLR->getType() == Type::DoubleTy)
assert(IsColorUsedArr[ NeighLR->getColor()+1 ]);
-
+
} else if (NeighLR->hasSuggestedColor() &&
NeighLR-> isSuggestedColorUsable() ) {
- // if the neighbour can use the suggested color
+ // if the neighbour can use the suggested color
assert(IsColorUsedArr[ NeighLR->getSuggestedColor() ]);
if (NeighLR->getType() == Type::DoubleTy)
assert(IsColorUsedArr[ NeighLR->getSuggestedColor()+1 ]);
@@ -242,9 +242,9 @@
// **NOTE: We don't check for call interferences in allocating suggested
// color in this class since ALL registers are volatile. If this fact
- // changes, we should change the following part
+ // changes, we should change the following part
//- see SparcV9IntRegClass::colorIGNode()
- //
+ //
if( LR->hasSuggestedColor() ) {
if( ! IsColorUsedArr[ LR->getSuggestedColor() ] ) {
LR->setColor( LR->getSuggestedColor() );
@@ -264,40 +264,40 @@
// cannot go there. By doing that, we provide more space for singles
// in f0 - f31
//
- if (LR->getType() == Type::DoubleTy)
+ if (LR->getType() == Type::DoubleTy)
ColorFound = findFloatColor( LR, 32, 64, IsColorUsedArr );
if (ColorFound >= 0) { // if we could find a color
- LR->setColor(ColorFound);
+ LR->setColor(ColorFound);
return;
- } else {
+ } else {
// if we didn't find a color because the LR was single precision or
// all f32-f63 range is filled, we try to allocate a register from
- // the f0 - f31 region
+ // the f0 - f31 region
unsigned SearchStart; // start pos of color in pref-order
//if this Node is between calls (i.e., no call interferences )
if (! isCallInterf) {
// start with volatiles (we can allocate volatiles safely)
- SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfAllRegs;
} else {
// start with non volatiles (no non-volatiles)
- SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
+ SearchStart = SparcV9FloatRegClass::StartOfNonVolatileRegs;
}
-
+
ColorFound = findFloatColor(LR, SearchStart, 32, IsColorUsedArr);
}
if (ColorFound >= 0) { // if we could find a color
- LR->setColor(ColorFound);
+ LR->setColor(ColorFound);
return;
- } else if (isCallInterf) {
+ } else if (isCallInterf) {
// We are here because there is a call interference and no non-volatile
// color could be found.
// Now try to allocate even a volatile color
- ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
+ ColorFound = findFloatColor(LR, SparcV9FloatRegClass::StartOfAllRegs,
SparcV9FloatRegClass::StartOfNonVolatileRegs,
IsColorUsedArr);
}
@@ -345,7 +345,7 @@
// entry in the array directly for float regs, and checks the pair [R,R+1]
// for double-precision registers
// It returns -1 if no unused color is found.
-//
+//
int SparcV9FloatRegClass::findUnusedColor(int RegTypeWanted,
const std::vector<bool> &IsColorUsedArr) const
{
@@ -369,13 +369,13 @@
// type of the Node (i.e., float/double)
//-----------------------------------------------------------------------------
-int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
+int SparcV9FloatRegClass::findFloatColor(const LiveRange *LR,
unsigned Start,
- unsigned End,
+ unsigned End,
const std::vector<bool> &IsColorUsedArr) const
{
- if (LR->getType() == Type::DoubleTy) {
- // find first unused color for a double
+ if (LR->getType() == Type::DoubleTy) {
+ // find first unused color for a double
assert(Start % 2 == 0 && "Odd register number could be used for double!");
for (unsigned c=Start; c < End ; c+= 2)
if (!IsColorUsedArr[c]) {
Index: llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.139 llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.140
--- llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp:1.139 Mon Mar 14 22:54:20 2005
+++ llvm/lib/Target/SparcV9/SparcV9RegInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9RegInfo.cpp - SparcV9 Target Register Information ----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file contains implementations of SparcV9 specific helper methods
@@ -44,8 +44,8 @@
MachineRegClassArr.push_back(new SparcV9IntCCRegClass(IntCCRegClassID));
MachineRegClassArr.push_back(new SparcV9FloatCCRegClass(FloatCCRegClassID));
MachineRegClassArr.push_back(new SparcV9SpecialRegClass(SpecialRegClassID));
-
- assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
+
+ assert(SparcV9FloatRegClass::StartOfNonVolatileRegs == 32 &&
"32 Float regs are used for float arg passing");
}
@@ -67,7 +67,7 @@
}
// Returns the register containing the return address.
-// It should be made sure that this register contains the return
+// It should be made sure that this register contains the return
// value when a return instruction is reached.
//
unsigned SparcV9RegInfo::getReturnAddressReg() const {
@@ -81,19 +81,19 @@
static const char * const IntRegNames[] = {
"o0", "o1", "o2", "o3", "o4", "o5", "o7",
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- "i0", "i1", "i2", "i3", "i4", "i5",
+ "i0", "i1", "i2", "i3", "i4", "i5",
"i6", "i7",
- "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
+ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
"o6"
-};
+};
const char * const SparcV9IntRegClass::getRegName(unsigned reg) const {
assert(reg < NumOfAllRegs);
return IntRegNames[reg];
}
-static const char * const FloatRegNames[] = {
- "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
+static const char * const FloatRegNames[] = {
+ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9",
"f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19",
"f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29",
"f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
@@ -107,7 +107,7 @@
return FloatRegNames[reg];
}
-static const char * const IntCCRegNames[] = {
+static const char * const IntCCRegNames[] = {
"xcc", "icc", "ccr"
};
@@ -116,7 +116,7 @@
return IntCCRegNames[reg];
}
-static const char * const FloatCCRegNames[] = {
+static const char * const FloatCCRegNames[] = {
"fcc0", "fcc1", "fcc2", "fcc3"
};
@@ -125,7 +125,7 @@
return FloatCCRegNames[reg];
}
-static const char * const SpecialRegNames[] = {
+static const char * const SpecialRegNames[] = {
"fsr"
};
@@ -168,12 +168,12 @@
// Get the register number for the specified argument #argNo,
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForIntArg(bool inCallee, bool isVarArgsCall,
unsigned argNo, unsigned& regClassId) const
@@ -187,12 +187,12 @@
// Get the register number for the specified FP argument #argNo,
// Use INT regs for FP args if this is a varargs call.
-//
+//
// Return value:
-// getInvalidRegNum(), if there is no int register available for the arg.
+// getInvalidRegNum(), if there is no int register available for the arg.
// regNum, otherwise (this is NOT the unified reg. num).
// regClassId is set to the register class ID.
-//
+//
int
SparcV9RegInfo::regNumForFPArg(unsigned regType,
bool inCallee, bool isVarArgsCall,
@@ -227,14 +227,14 @@
const Type* type) const
{
switch (regClassID) {
- case IntRegClassID: return IntRegType;
+ case IntRegClassID: return IntRegType;
case FloatRegClassID:
if (type == Type::FloatTy) return FPSingleRegType;
else if (type == Type::DoubleTy) return FPDoubleRegType;
assert(0 && "Unknown type in FloatRegClass"); return 0;
- case IntCCRegClassID: return IntCCRegType;
- case FloatCCRegClassID: return FloatCCRegType;
- case SpecialRegClassID: return SpecialRegType;
+ case IntCCRegClassID: return IntCCRegType;
+ case FloatCCRegClassID: return FloatCCRegType;
+ case SpecialRegClassID: return SpecialRegType;
default: assert( 0 && "Unknown reg class ID"); return 0;
}
}
@@ -251,7 +251,7 @@
int SparcV9RegInfo::getRegType(int unifiedRegNum) const
{
- if (unifiedRegNum < 32)
+ if (unifiedRegNum < 32)
return IntRegType;
else if (unifiedRegNum < (32 + 32))
return FPSingleRegType;
@@ -259,11 +259,11 @@
return FPDoubleRegType;
else if (unifiedRegNum < (64+32+3))
return IntCCRegType;
- else if (unifiedRegNum < (64+32+3+4))
- return FloatCCRegType;
- else if (unifiedRegNum < (64+32+3+4+1))
- return SpecialRegType;
- else
+ else if (unifiedRegNum < (64+32+3+4))
+ return FloatCCRegType;
+ else if (unifiedRegNum < (64+32+3+4+1))
+ return SpecialRegType;
+ else
assert(0 && "Invalid unified register number in getRegType");
return 0;
}
@@ -275,22 +275,22 @@
bool isCCReg) const {
Type::TypeID ty = type->getTypeID();
unsigned res;
-
+
// FIXME: Comparing types like this isn't very safe...
if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
(ty == Type::FunctionTyID) || (ty == Type::PointerTyID) )
res = IntRegClassID; // sparc int reg (ty=0: void)
else if (ty <= Type::DoubleTyID)
res = FloatRegClassID; // sparc float reg class
- else {
+ else {
//std::cerr << "TypeID: " << ty << "\n";
assert(0 && "Cannot resolve register class for type");
return 0;
}
-
+
if (isCCReg)
- return res + 2; // corresponding condition code register
- else
+ return res + 2; // corresponding condition code register
+ else
return res;
}
@@ -312,16 +312,16 @@
// Suggests a register for the ret address in the RET machine instruction.
// We always suggest %i7 by convention.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetAddr(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert(target.getInstrInfo()->isReturn(RetMI->getOpcode()));
-
+
// return address is always mapped to i7 so set it immediately
RetMI->SetRegForOperand(0, getUnifiedRegNum(IntRegClassID,
SparcV9IntRegClass::i7));
-
- // Possible Optimization:
+
+ // Possible Optimization:
// Instead of setting the color, we can suggest one. In that case,
// we have to test later whether it received the suggested color.
// In that case, a LR has to be created at the start of method.
@@ -330,8 +330,8 @@
// MachineOperand & MO = RetMI->getOperand(0);
// const Value *RetAddrVal = MO.getVRegValue();
// assert( RetAddrVal && "LR for ret address must be created at start");
- // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
- // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
+ // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
+ // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
// SparcV9IntRegOrdr::i7) );
}
@@ -344,7 +344,7 @@
SparcV9RegInfo::suggestReg4CallAddr(MachineInstr * CallMI,
LiveRangeInfo& LRI) const
{
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
const Value *RetAddrVal = argDesc->getReturnAddrReg();
assert(RetAddrVal && "INTERNAL ERROR: Return address value is required");
@@ -359,18 +359,18 @@
//---------------------------------------------------------------------------
-// This method will suggest colors to incoming args to a method.
-// According to the SparcV9 ABI, the first 6 incoming args are in
+// This method will suggest colors to incoming args to a method.
+// According to the SparcV9 ABI, the first 6 incoming args are in
// %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
// If the arg is passed on stack due to the lack of regs, NOTHING will be
// done - it will be colored (or spilled) as a normal live range.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
- LiveRangeInfo& LRI) const
+void SparcV9RegInfo::suggestRegs4MethodArgs(const Function *Meth,
+ LiveRangeInfo& LRI) const
{
// Check if this is a varArgs function. needed for choosing regs.
bool isVarArgs = isVarArgsFunction(Meth->getType());
-
+
// Count the arguments, *ignoring* whether they are int or FP args.
// Use this common arg numbering to pick the right int or fp register.
unsigned argNo=0;
@@ -378,15 +378,15 @@
I != E; ++I, ++argNo) {
LiveRange *LR = LRI.getLiveRangeForValue(I);
assert(LR && "No live range found for method arg");
-
+
unsigned regType = getRegTypeForLR(LR);
unsigned regClassIDOfArgReg = BadRegClass; // for chosen reg (unused)
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs, argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs, argNo,
- regClassIDOfArgReg);
-
+ regClassIDOfArgReg);
+
if (regNum != getInvalidRegNum())
LR->setSuggestedColor(regNum);
}
@@ -398,7 +398,7 @@
// the correct hardware registers if they did not receive the correct
// (suggested) color through graph coloring.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
+void SparcV9RegInfo::colorMethodArgs(const Function *Meth,
LiveRangeInfo &LRI,
std::vector<MachineInstr*>& InstrnsBefore,
std::vector<MachineInstr*>& InstrnsAfter) const {
@@ -418,25 +418,25 @@
unsigned regType = getRegTypeForLR(LR);
unsigned RegClassID = LR->getRegClassID();
-
+
// Find whether this argument is coming in a register (if not, on stack)
// Also find the correct register the argument must use (UniArgReg)
//
bool isArgInReg = false;
unsigned UniArgReg = getInvalidRegNum(); // reg that LR MUST be colored with
unsigned regClassIDOfArgReg = BadRegClass; // reg class of chosen reg
-
+
int regNum = (regType == IntRegType)
? regNumForIntArg(/*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ true, isVarArgs,
argNo, regClassIDOfArgReg);
-
+
if(regNum != getInvalidRegNum()) {
isArgInReg = true;
UniArgReg = getUnifiedRegNum( regClassIDOfArgReg, regNum);
}
-
+
if( ! LR->isMarkedForSpill() ) { // if this arg received a register
unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
@@ -446,31 +446,31 @@
if( UniLRReg == UniArgReg )
continue;
- // We are here because the LR did not receive the suggested
+ // We are here because the LR did not receive the suggested
// but LR received another register.
- // Now we have to copy the %i reg (or stack pos of arg)
+ // Now we have to copy the %i reg (or stack pos of arg)
// to the register the LR was colored with.
-
+
// if the arg is coming in UniArgReg register, it MUST go into
// the UniLRReg register
//
if( isArgInReg ) {
if( regClassIDOfArgReg != RegClassID ) {
// NOTE: This code has not been well-tested.
-
+
// It is a variable argument call: the float reg must go in a %o reg.
// We have to move an int reg to a float reg via memory.
- //
+ //
assert(isVarArgs &&
- RegClassID == FloatRegClassID &&
+ RegClassID == FloatRegClassID &&
regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
+
int TmpOff = MachineFunction::get(Meth).getInfo<SparcV9FunctionInfo>()->pushTempValue(
getSpilledRegSize(regType));
cpReg2MemMI(InstrnsBefore,
UniArgReg, getFramePointer(), TmpOff, IntRegType);
-
+
cpMem2RegMI(InstrnsBefore,
getFramePointer(), TmpOff, UniLRReg, regType);
}
@@ -501,10 +501,10 @@
cpMem2RegMI(InstrnsBefore,
getFramePointer(), offsetFromFP, UniLRReg, regType);
}
-
+
} // if LR received a color
- else {
+ else {
// Now, the LR did not receive a color. But it has a stack offset for
// spilling.
@@ -512,18 +512,18 @@
// that on to the stack pos of LR
if( isArgInReg ) {
-
+
if( regClassIDOfArgReg != RegClassID ) {
assert(0 &&
"FP arguments to a varargs function should be explicitly "
"copied to/from int registers by instruction selection!");
-
+
// It must be a float arg for a variable argument call, which
// must come in a %o reg. Move the int reg to the stack.
- //
+ //
assert(isVarArgs && regClassIDOfArgReg == IntRegClassID &&
"This should only be an Int register for an FP argument");
-
+
cpReg2MemMI(InstrnsBefore, UniArgReg,
getFramePointer(), LR->getSpillOffFromFP(), IntRegType);
}
@@ -535,12 +535,12 @@
else {
- // Now the arg is coming on stack. Since the LR did NOT
+ // Now the arg is coming on stack. Since the LR did NOT
// received a register as well, it is allocated a stack position. We
// can simply change the stack position of the LR. We can do this,
// since this method is called before any other method that makes
// uses of the stack pos of the LR (e.g., updateMachineInstr)
- //
+ //
const TargetFrameInfo& frameInfo = *target.getFrameInfo();
int offsetFromFP =
frameInfo.getIncomingArgOffset(MachineFunction::get(Meth),
@@ -555,7 +555,7 @@
assert(argSize <= slotSize && "Insufficient slot size!");
offsetFromFP += slotSize - argSize;
}
-
+
LR->modifySpillOffFromFP( offsetFromFP );
}
@@ -571,18 +571,18 @@
// This method is called before graph coloring to suggest colors to the
// outgoing call args and the return value of the call.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
+void SparcV9RegInfo::suggestRegs4CallArgs(MachineInstr *CallMI,
LiveRangeInfo& LRI) const {
assert ( (target.getInstrInfo())->isCall(CallMI->getOpcode()) );
- CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
-
+ CallArgsDescriptor* argDesc = CallArgsDescriptor::get(CallMI);
+
suggestReg4CallAddr(CallMI, LRI);
// First color the return value of the call instruction, if any.
// The return value will be in %o0 if the value is an integer type,
// or in %f0 if the value is a float type.
- //
+ //
if (const Value *RetVal = argDesc->getReturnValue()) {
LiveRange *RetValLR = LRI.getLiveRangeForValue(RetVal);
assert(RetValLR && "No LR for return Value of call!");
@@ -590,9 +590,9 @@
unsigned RegClassID = RetValLR->getRegClassID();
// now suggest a register depending on the register class of ret arg
- if( RegClassID == IntRegClassID )
+ if( RegClassID == IntRegClassID )
RetValLR->setSuggestedColor(SparcV9IntRegClass::o0);
- else if (RegClassID == FloatRegClassID )
+ else if (RegClassID == FloatRegClassID )
RetValLR->setSuggestedColor(SparcV9FloatRegClass::f0 );
else assert( 0 && "Unknown reg class for return value of call\n");
}
@@ -603,14 +603,14 @@
// Now, go thru call args - implicit operands of the call MI
unsigned NumOfCallArgs = argDesc->getNumArgs();
-
+
for(unsigned argNo=0, i=0, intArgNo=0, fpArgNo=0;
- i < NumOfCallArgs; ++i, ++argNo) {
+ i < NumOfCallArgs; ++i, ++argNo) {
const Value *CallArg = argDesc->getArgInfo(i).getArgVal();
-
+
// get the LR of call operand (parameter)
- LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
+ LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
if (!LR)
continue; // no live ranges for constants and labels
@@ -625,8 +625,8 @@
? regNumForIntArg(/*inCallee*/ false, /*isVarArgs*/ false,
argNo, regClassIDOfArgReg)
: regNumForFPArg(regType, /*inCallee*/ false, /*isVarArgs*/ false,
- argNo, regClassIDOfArgReg);
-
+ argNo, regClassIDOfArgReg);
+
// If a register could be allocated, use it.
// If not, do NOTHING as this will be colored as a normal value.
if(regNum != getInvalidRegNum())
@@ -639,7 +639,7 @@
// this method is called for an LLVM return instruction to identify which
// values will be returned from this method and to suggest colors.
//---------------------------------------------------------------------------
-void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
+void SparcV9RegInfo::suggestReg4RetValue(MachineInstr *RetMI,
LiveRangeInfo& LRI) const {
assert( target.getInstrInfo()->isReturn( RetMI->getOpcode() ) );
@@ -688,14 +688,14 @@
unsigned SrcReg,
unsigned DestReg,
int RegType) const {
- assert( ((int)SrcReg != getInvalidRegNum()) &&
+ assert( ((int)SrcReg != getInvalidRegNum()) &&
((int)DestReg != getInvalidRegNum()) &&
"Invalid Register");
-
+
MachineInstr * MI = NULL;
-
+
switch( RegType ) {
-
+
case IntCCRegType:
if (getRegType(DestReg) == IntRegType) {
// copy intCC reg to int reg
@@ -715,16 +715,16 @@
MachineOperand::Def));
}
break;
-
- case FloatCCRegType:
+
+ case FloatCCRegType:
assert(0 && "Cannot copy FPCC register to any other register");
break;
-
+
case IntRegType:
MI = BuildMI(V9::ADDr, 3).addMReg(SrcReg).addMReg(getZeroRegNum())
.addMReg(DestReg, MachineOperand::Def);
break;
-
+
case FPSingleRegType:
MI = BuildMI(V9::FMOVS, 2).addMReg(SrcReg)
.addMReg(DestReg, MachineOperand::Def);
@@ -739,7 +739,7 @@
assert(0 && "Unknown RegType");
break;
}
-
+
if (MI)
mvec.push_back(MI);
}
@@ -894,7 +894,7 @@
MI = BuildMI(V9::WRCCRr, 3).addMReg(scratchReg).addMReg(SparcV9::g0)
.addMReg(SparcV9::ccr, MachineOperand::Def);
break;
-
+
case SpecialRegType: // used only for %fsr itself
case FloatCCRegType: {
if (useImmediateOffset)
@@ -956,13 +956,13 @@
std::cerr << " - could not find a color\n";
return;
}
-
+
// if a color is found
std::cerr << " colored with color "<< LR->getColor();
unsigned uRegName = getUnifiedRegNum(RegClassID, LR->getColor());
-
+
std::cerr << "[";
std::cerr<< getUnifiedRegName(uRegName);
if (RegClassID == FloatRegClassID && LR->getType() == Type::DoubleTy)
Index: llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.4 llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.5
--- llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp:1.4 Sun Aug 15 17:15:09 2004
+++ llvm/lib/Target/SparcV9/SparcV9RegisterInfo.cpp Thu Apr 21 18:25:42 2005
@@ -20,7 +20,7 @@
// TableGen to generate the register file description automatically.
// It consists of register classes and register class instances
// for the SparcV9 target.
-//
+//
// FIXME: the alignments listed here are wild guesses.
//
//===----------------------------------------------------------------------===//
@@ -295,7 +295,7 @@
abort ();
}
-void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI)
+void SparcV9RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI)
const {
abort ();
}
Index: llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.13 llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.14
--- llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp:1.13 Thu Jul 1 23:57:35 2004
+++ llvm/lib/Target/SparcV9/SparcV9SchedInfo.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===-- SparcV9SchedInfo.cpp ----------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Describe the scheduling characteristics of the UltraSparc IIi.
@@ -28,7 +28,7 @@
(see pg. 327).
** Don't put a branch in a group that crosses a 32-byte boundary!
An artificial branch is inserted after every 32 bytes, and having
- another branch will force the group to be broken into 2 groups.
+ another branch will force the group to be broken into 2 groups.
iTLB rules:
-- Don't let a loop span two memory pages, if possible
@@ -73,8 +73,8 @@
-- Several instructions must be issued in a single-instruction group:
MOVcc or MOVr, MULs/x and DIVs/x, SAVE/RESTORE, many others
-- A CALL or JMPL breaks a group, ie, is not combined with subsequent instrs.
---
---
+--
+--
Branch delay slot scheduling rules:
-- A CTI couple (two back-to-back CTI instructions in the dynamic stream)
@@ -100,8 +100,8 @@
static const CPUResource FPMIssueSlots( "FP Instr Slot 2", 1);
// IEUN instructions can use either Alu and should use IAluN.
-// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
-// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
+// IEU0 instructions must use Alu 1 and should use both IAluN and IAlu0.
+// IEU1 instructions must use Alu 2 and should use both IAluN and IAlu1.
static const CPUResource IAluN("Int ALU 1or2", 2);
static const CPUResource IAlu0("Int ALU 1", 1);
static const CPUResource IAlu1("Int ALU 2", 1);
@@ -130,7 +130,7 @@
//---------------------------------------------------------------------------
// const InstrClassRUsage SparcV9RUsageDesc[]
-//
+//
// Purpose:
// Resource usage information for instruction in each scheduling class.
// The InstrRUsage Objects for individual classes are specified first.
@@ -141,15 +141,15 @@
static const InstrClassRUsage NoneClassRUsage = {
SPARC_NONE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 4,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 0,
/* V[] */ {
/*Cycle G */
@@ -165,15 +165,15 @@
static const InstrClassRUsage IEUNClassRUsage = {
SPARC_IEUN,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 3,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -190,15 +190,15 @@
static const InstrClassRUsage IEU0ClassRUsage = {
SPARC_IEU0,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -216,15 +216,15 @@
static const InstrClassRUsage IEU1ClassRUsage = {
SPARC_IEU1,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -242,15 +242,15 @@
static const InstrClassRUsage FPMClassRUsage = {
SPARC_FPM,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -267,15 +267,15 @@
static const InstrClassRUsage FPAClassRUsage = {
SPARC_FPA,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 7,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -292,15 +292,15 @@
static const InstrClassRUsage LDClassRUsage = {
SPARC_LD,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2, },
-
+
/*numEntries*/ 6,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -319,15 +319,15 @@
static const InstrClassRUsage STClassRUsage = {
SPARC_ST,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 3,
/* feasibleSlots[] */ { 0, 1, 2 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -345,22 +345,22 @@
static const InstrClassRUsage CTIClassRUsage = {
SPARC_CTI,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ false,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 4,
/* feasibleSlots[] */ { 0, 1, 2, 3 },
-
+
/*numEntries*/ 4,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
{ CTIIssueSlots.rid, 0, 1 },
/*Cycle E */ { IAlu0.rid, 1, 1 },
/*Cycles E-C */ { CTIDelayCycle.rid, 1, 2 }
- /*Cycle C */
+ /*Cycle C */
/*Cycle N1*/
/*Cycle N1*/
/*Cycle N1*/
@@ -371,15 +371,15 @@
static const InstrClassRUsage SingleClassRUsage = {
SPARC_SINGLE,
/*totCycles*/ 7,
-
+
/* maxIssueNum */ 1,
/* isSingleIssue */ true,
/* breaksGroup */ false,
/* numBubbles */ 0,
-
+
/*numSlots*/ 1,
/* feasibleSlots[] */ { 0 },
-
+
/*numEntries*/ 5,
/* V[] */ {
/*Cycle G */ { AllIssueSlots.rid, 0, 1 },
@@ -413,7 +413,7 @@
//---------------------------------------------------------------------------
// const InstrIssueDelta SparcV9InstrIssueDeltas[]
-//
+//
// Purpose:
// Changes to issue restrictions information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
@@ -461,7 +461,7 @@
//{ V9::RETRY, true, true, 0 },
//{ V9::TCC, true, true, 0 },
//{ V9::SHUTDOWN, true, true, 0 },
-
+
// Special cases for breaking group *before*
// CURRENTLY NOT SUPPORTED!
{ V9::CALL, false, false, 0 },
@@ -469,7 +469,7 @@
{ V9::JMPLCALLi, false, false, 0 },
{ V9::JMPLRETr, false, false, 0 },
{ V9::JMPLRETi, false, false, 0 },
-
+
// Special cases for breaking the group *after*
{ V9::MULXr, true, true, (4+34)/2 },
{ V9::MULXi, true, true, (4+34)/2 },
@@ -480,7 +480,7 @@
{ V9::FSQRTD, false, true, 0 },
{ V9::FSQRTQ, false, true, 0 },
//{ V9::FCMP{LE,GT,NE,EQ}, false, true, 0 },
-
+
// Instructions that introduce bubbles
//{ V9::MULScc, true, true, 2 },
//{ V9::SMULcc, true, true, (4+18)/2 },
@@ -503,7 +503,7 @@
//---------------------------------------------------------------------------
// const InstrRUsageDelta SparcV9InstrUsageDeltas[]
-//
+//
// Purpose:
// Changes to resource usage information in InstrClassRUsage for
// instructions that differ from other instructions in their class.
@@ -513,22 +513,22 @@
// MachineOpCode, Resource, Start cycle, Num cycles
- //
+ //
// JMPL counts as a load/store instruction for issue!
//
{ V9::JMPLCALLr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLCALLi, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETr, LSIssueSlots.rid, 0, 1 },
{ V9::JMPLRETi, LSIssueSlots.rid, 0, 1 },
-
- //
+
+ //
// Many instructions cannot issue for the next 2 cycles after an FCMP
// We model that with a fake resource FCMPDelayCycle.
- //
+ //
{ V9::FCMPS, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPD, FCMPDelayCycle.rid, 1, 3 },
{ V9::FCMPQ, FCMPDelayCycle.rid, 1, 3 },
-
+
{ V9::MULXr, FCMPDelayCycle.rid, 1, 1 },
{ V9::MULXi, FCMPDelayCycle.rid, 1, 1 },
{ V9::SDIVXr, FCMPDelayCycle.rid, 1, 1 },
@@ -547,11 +547,11 @@
{ V9::FMOVRSNZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGZ, FCMPDelayCycle.rid, 1, 1 },
{ V9::FMOVRSGEZ,FCMPDelayCycle.rid, 1, 1 },
-
- //
+
+ //
// Some instructions are stalled in the GROUP stage if a CTI is in
// the E or C stage. We model that with a fake resource CTIDelayCycle.
- //
+ //
{ V9::LDDFr, CTIDelayCycle.rid, 1, 1 },
{ V9::LDDFi, CTIDelayCycle.rid, 1, 1 },
//{ V9::LDDA, CTIDelayCycle.rid, 1, 1 },
@@ -563,7 +563,7 @@
//{ V9::CASA, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASX, CTIDelayCycle.rid, 1, 1 },
//{ V9::CASXA, CTIDelayCycle.rid, 1, 1 },
-
+
//
// Signed int loads of less than dword size return data in cycle N1 (not C)
// and put all loads in consecutive cycles into delayed load return mode.
@@ -572,12 +572,12 @@
{ V9::LDSBr, LdReturn.rid, 3, 1 },
{ V9::LDSBi, LdReturn.rid, 2, -1 },
{ V9::LDSBi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSHr, LdReturn.rid, 2, -1 },
{ V9::LDSHr, LdReturn.rid, 3, 1 },
{ V9::LDSHi, LdReturn.rid, 2, -1 },
{ V9::LDSHi, LdReturn.rid, 3, 1 },
-
+
{ V9::LDSWr, LdReturn.rid, 2, -1 },
{ V9::LDSWr, LdReturn.rid, 3, 1 },
{ V9::LDSWi, LdReturn.rid, 2, -1 },
@@ -589,7 +589,7 @@
// Together with their single-issue requirement, this means all four issue
// slots are effectively blocked for those cycles, plus the issue cycle.
// This does not increase the latency of the instruction itself.
- //
+ //
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
{ V9::RDCCR, AllIssueSlots.rid, 0, 5 },
@@ -597,96 +597,96 @@
#undef EXPLICIT_BUBBLES_NEEDED
#ifdef EXPLICIT_BUBBLES_NEEDED
- //
+ //
// MULScc inserts one bubble.
// This means it breaks the current group (captured in UltraSparcV9SchedInfo)
// *and occupies all issue slots for the next cycle
- //
+ //
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
//{ V9::MULScc, AllIssueSlots.rid, 2, 2-1 },
-
- //
+
+ //
// SMULcc inserts between 4 and 18 bubbles, depending on #leading 0s in rs1.
// We just model this with a simple average.
- //
+ //
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
//{ V9::SMULcc, AllIssueSlots.rid, 2, ((4+18)/2)-1 },
-
+
// SMULcc inserts between 4 and 19 bubbles, depending on #leading 0s in rs1.
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
//{ V9::UMULcc, AllIssueSlots.rid, 2, ((4+19)/2)-1 },
-
- //
+
+ //
// MULX inserts between 4 and 34 bubbles, depending on #leading 0s in rs1.
- //
+ //
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
{ V9::MULX, AllIssueSlots.rid, 2, ((4+34)/2)-1 },
-
- //
+
+ //
// SDIVcc inserts 36 bubbles.
- //
+ //
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
//{ V9::SDIVcc, AllIssueSlots.rid, 2, 36-1 },
-
+
// UDIVcc inserts 37 bubbles.
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
//{ V9::UDIVcc, AllIssueSlots.rid, 2, 37-1 },
-
- //
+
+ //
// SDIVX inserts 68 bubbles.
- //
+ //
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::SDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// UDIVX inserts 68 bubbles.
- //
+ //
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
{ V9::UDIVX, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WR inserts 4 bubbles.
- //
+ //
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// WRPR inserts 4 bubbles.
- //
+ //
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
//{ V9::WRPR, AllIssueSlots.rid, 2, 68-1 },
-
- //
+
+ //
// DONE inserts 9 bubbles.
- //
+ //
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
//{ V9::DONE, AllIssueSlots.rid, 2, 9-1 },
-
- //
+
+ //
// RETRY inserts 9 bubbles.
- //
+ //
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
//{ V9::RETRY, AllIssueSlots.rid, 2, 9-1 },
@@ -713,7 +713,7 @@
// branch. The group will stall until the load returns.
//11. Single-prec. FP loads lock 2 registers, for dependency checking.
//
-//
+//
// Additional delays we cannot or will not capture:
// 1. If DCTI is last word of cache line, it is delayed until next line can be
// fetched. Also, other DCTI alignment-related delays (pg 352)
@@ -726,8 +726,8 @@
//---------------------------------------------------------------------------
-// class SparcV9SchedInfo
-//
+// class SparcV9SchedInfo
+//
// Purpose:
// Scheduling information for the UltraSPARC.
// Primarily just initializes machine-dependent parameters in
@@ -746,7 +746,7 @@
{
maxNumIssueTotal = 4;
longestIssueConflict = 0; // computed from issuesGaps[]
-
+
// must be called after above parameters are initialized.
initializeResources();
}
@@ -756,6 +756,6 @@
{
// Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps
TargetSchedInfo::initializeResources();
-
+
// Machine-dependent fixups go here. None for now.
}
Index: llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.14 llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.15
--- llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp:1.14 Sun Sep 19 23:46:39 2004
+++ llvm/lib/Target/SparcV9/SparcV9StackSlots.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9StackSlots.cpp - Add empty stack slots to functions ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass adds 2 empty slots at the top of function stack. These two slots
@@ -26,19 +26,19 @@
const TargetMachine &Target;
public:
StackSlots(const TargetMachine &T) : Target(T) {}
-
+
const char *getPassName() const {
return "Stack Slot Insertion for profiling code";
}
-
+
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
}
-
+
bool runOnMachineFunction(MachineFunction &MF) {
const Type *PtrInt = PointerType::get(Type::IntTy);
unsigned Size = Target.getTargetData().getTypeSize(PtrInt);
-
+
Value *V = Constant::getNullValue(Type::IntTy);
MF.getInfo<SparcV9FunctionInfo>()->allocateLocalVar(V, 2*Size);
return true;
Index: llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.134 llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.135
--- llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp:1.134 Wed Feb 23 20:14:44 2005
+++ llvm/lib/Target/SparcV9/SparcV9TargetMachine.cpp Thu Apr 21 18:25:42 2005
@@ -1,16 +1,16 @@
//===-- SparcV9TargetMachine.cpp - SparcV9 Target Machine Implementation --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// Primary interface to machine description for the UltraSPARC. Primarily just
// initializes machine-dependent parameters in class TargetMachine, and creates
// machine-dependent subclasses for classes such as TargetInstrInfo.
-//
+//
//===----------------------------------------------------------------------===//
#include "llvm/Function.h"
@@ -23,7 +23,7 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
-#include "MappingInfo.h"
+#include "MappingInfo.h"
#include "MachineFunctionInfo.h"
#include "MachineCodeForInstruction.h"
#include "SparcV9Internals.h"
@@ -63,7 +63,7 @@
cl::init(false),
cl::desc("Emit LLVM-to-MachineCode mapping info to assembly"));
- cl::opt<bool> EnableModSched("enable-modsched",
+ cl::opt<bool> EnableModSched("enable-modsched",
cl::desc("Enable modulo scheduling pass instead of local scheduling"), cl::Hidden);
// Register the target.
@@ -103,11 +103,11 @@
TargetMachine &Target;
public:
ConstructMachineFunction(TargetMachine &T) : Target(T) {}
-
+
const char *getPassName() const {
return "ConstructMachineFunction";
}
-
+
bool runOnFunction(Function &F) {
MachineFunction::construct(&F, Target).getInfo<SparcV9FunctionInfo>()->CalculateArgSize();
return false;
@@ -116,24 +116,24 @@
struct DestroyMachineFunction : public FunctionPass {
const char *getPassName() const { return "DestroyMachineFunction"; }
-
+
static void freeMachineCode(Instruction &I) {
MachineCodeForInstruction::destroy(&I);
}
-
+
bool runOnFunction(Function &F) {
for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
for (BasicBlock::iterator I = FI->begin(), E = FI->end(); I != E; ++I)
MachineCodeForInstruction::get(I).dropAllReferences();
-
+
for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
for_each(FI->begin(), FI->end(), freeMachineCode);
-
+
MachineFunction::destruct(&F);
return false;
}
};
-
+
FunctionPass *createMachineCodeConstructionPass(TargetMachine &Target) {
return new ConstructMachineFunction(Target);
}
@@ -164,13 +164,13 @@
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
// FIXME: implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
-
+
// decompose multi-dimensional array references into single-dim refs
PM.add(createDecomposeMultiDimRefsPass());
@@ -189,7 +189,7 @@
// Insert empty stackslots in the stack frame of each function
// so %fp+offset-8 and %fp+offset-16 are empty slots now!
PM.add(createStackSlotsPass(*this));
-
+
PM.add(createSparcV9BurgInstSelector(*this));
if (!DisableSched)
@@ -201,7 +201,7 @@
//Use ModuloScheduling if enabled, otherwise use local scheduling if not disabled.
if(EnableModSched)
PM.add(createModuloSchedulingPass(*this));
-
+
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr, "Before reg alloc:\n"));
@@ -236,7 +236,7 @@
// Emit bytecode to the assembly file into its special section next
if (EmitMappingInfo)
PM.add(createBytecodeAsmPrinterPass(Out));
-
+
return false;
}
@@ -249,13 +249,13 @@
// Replace malloc and free instructions with library calls.
PM.add(createLowerAllocationsPass());
-
+
// FIXME: implement the switch instruction in the instruction selector.
PM.add(createLowerSwitchPass());
// FIXME: implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
-
+
// decompose multi-dimensional array references into single-dim refs
PM.add(createDecomposeMultiDimRefsPass());
Index: llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp
diff -u llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.4 llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.5
--- llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp:1.4 Thu Mar 17 09:37:18 2005
+++ llvm/lib/Target/SparcV9/SparcV9TmpInstr.cpp Thu Apr 21 18:25:42 2005
@@ -1,10 +1,10 @@
//===- SparcV9TmpInstr.cpp - SparcV9 Intermediate Value class -------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Methods of class for temporary intermediate values used within the current
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