[llvm-commits] CVS: llvm/lib/CodeGen/AsmPrinter.cpp BranchFolding.cpp IntrinsicLowering.cpp LiveIntervalAnalysis.cpp LiveInterval.cpp LiveVariables.cpp MachineBasicBlock.cpp MachineCodeEmitter.cpp MachineFunction.cpp MachineInstr.cpp Passes.cpp PHIElimination.cpp PrologEpilogInserter.cpp RegAllocLinearScan.cpp RegAllocLocal.cpp RegAllocSimple.cpp TwoAddressInstructionPass.cpp UnreachableBlockElim.cpp ValueTypes.cpp VirtRegMap.cpp
Misha Brukman
brukman at cs.uiuc.edu
Thu Apr 21 15:33:44 PDT 2005
Changes in directory llvm/lib/CodeGen:
AsmPrinter.cpp updated: 1.16 -> 1.17
BranchFolding.cpp updated: 1.7 -> 1.8
IntrinsicLowering.cpp updated: 1.25 -> 1.26
LiveIntervalAnalysis.cpp updated: 1.138 -> 1.139
LiveInterval.cpp updated: 1.19 -> 1.20
LiveVariables.cpp updated: 1.48 -> 1.49
MachineBasicBlock.cpp updated: 1.24 -> 1.25
MachineCodeEmitter.cpp updated: 1.22 -> 1.23
MachineFunction.cpp updated: 1.77 -> 1.78
MachineInstr.cpp updated: 1.106 -> 1.107
Passes.cpp updated: 1.14 -> 1.15
PHIElimination.cpp updated: 1.33 -> 1.34
PrologEpilogInserter.cpp updated: 1.41 -> 1.42
RegAllocLinearScan.cpp updated: 1.107 -> 1.108
RegAllocLocal.cpp updated: 1.71 -> 1.72
RegAllocSimple.cpp updated: 1.62 -> 1.63
TwoAddressInstructionPass.cpp updated: 1.29 -> 1.30
UnreachableBlockElim.cpp updated: 1.5 -> 1.6
ValueTypes.cpp updated: 1.2 -> 1.3
VirtRegMap.cpp updated: 1.36 -> 1.37
---
Log message:
Remove trailing whitespace
---
Diffs of the changes: (+121 -121)
AsmPrinter.cpp | 12 ++++++------
BranchFolding.cpp | 6 +++---
IntrinsicLowering.cpp | 12 ++++++------
LiveInterval.cpp | 4 ++--
LiveIntervalAnalysis.cpp | 4 ++--
LiveVariables.cpp | 20 ++++++++++----------
MachineBasicBlock.cpp | 2 +-
MachineCodeEmitter.cpp | 14 +++++++-------
MachineFunction.cpp | 2 +-
MachineInstr.cpp | 36 ++++++++++++++++++------------------
PHIElimination.cpp | 28 ++++++++++++++--------------
Passes.cpp | 4 ++--
PrologEpilogInserter.cpp | 24 ++++++++++++------------
RegAllocLinearScan.cpp | 8 ++++----
RegAllocLocal.cpp | 2 +-
RegAllocSimple.cpp | 24 ++++++++++++------------
TwoAddressInstructionPass.cpp | 8 ++++----
UnreachableBlockElim.cpp | 6 +++---
ValueTypes.cpp | 4 ++--
VirtRegMap.cpp | 22 +++++++++++-----------
20 files changed, 121 insertions(+), 121 deletions(-)
Index: llvm/lib/CodeGen/AsmPrinter.cpp
diff -u llvm/lib/CodeGen/AsmPrinter.cpp:1.16 llvm/lib/CodeGen/AsmPrinter.cpp:1.17
--- llvm/lib/CodeGen/AsmPrinter.cpp:1.16 Sat Apr 2 06:21:50 2005
+++ llvm/lib/CodeGen/AsmPrinter.cpp Thu Apr 21 17:33:33 2005
@@ -148,7 +148,7 @@
O << "\"";
for (unsigned i = 0; i != CVA->getNumOperands(); ++i) {
- unsigned char C =
+ unsigned char C =
(unsigned char)cast<ConstantInt>(CVA->getOperand(i))->getRawValue();
if (C == '"') {
@@ -178,7 +178,7 @@
/// emitGlobalConstant - Print a general LLVM constant to the .s file.
///
-void AsmPrinter::emitGlobalConstant(const Constant *CV) {
+void AsmPrinter::emitGlobalConstant(const Constant *CV) {
const TargetData &TD = TM.getTargetData();
if (CV->isNullValue() || isa<UndefValue>(CV)) {
@@ -253,7 +253,7 @@
int32_t UVal;
} U;
U.FVal = (float)Val;
-
+
O << Data32bitsDirective << U.UVal << "\t" << CommentString
<< " float " << Val << "\n";
return;
@@ -261,7 +261,7 @@
} else if (CV->getType() == Type::ULongTy || CV->getType() == Type::LongTy) {
if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
uint64_t Val = CI->getRawValue();
-
+
if (Data64bitsDirective)
O << Data64bitsDirective << Val << "\n";
else if (TD.isBigEndian()) {
@@ -285,7 +285,7 @@
const Type *type = CV->getType();
switch (type->getTypeID()) {
- case Type::BoolTyID:
+ case Type::BoolTyID:
case Type::UByteTyID: case Type::SByteTyID:
O << Data8bitsDirective;
break;
@@ -301,7 +301,7 @@
case Type::UIntTyID: case Type::IntTyID:
O << Data32bitsDirective;
break;
- case Type::ULongTyID: case Type::LongTyID:
+ case Type::ULongTyID: case Type::LongTyID:
assert (0 && "Should have already output double-word constant.");
case Type::FloatTyID: case Type::DoubleTyID:
assert (0 && "Should have already output floating point constant.");
Index: llvm/lib/CodeGen/BranchFolding.cpp
diff -u llvm/lib/CodeGen/BranchFolding.cpp:1.7 llvm/lib/CodeGen/BranchFolding.cpp:1.8
--- llvm/lib/CodeGen/BranchFolding.cpp:1.7 Wed Sep 1 17:55:35 2004
+++ llvm/lib/CodeGen/BranchFolding.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- BranchFolding.cpp - Fold machine code branch instructions ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass forwards branches to unconditional branches to make them branch
@@ -158,7 +158,7 @@
assert(Br->getNumOperands() == 1 && Br->getOperand(0).isMachineBasicBlock()
&& "Uncond branch should take one MBB argument!");
MachineBasicBlock *Dest = Br->getOperand(0).getMachineBasicBlock();
-
+
while (!MBB->pred_empty()) {
MachineBasicBlock *Pred = *(MBB->pred_end()-1);
ReplaceUsesOfBlockWith(Pred, MBB, Dest, TII);
Index: llvm/lib/CodeGen/IntrinsicLowering.cpp
diff -u llvm/lib/CodeGen/IntrinsicLowering.cpp:1.25 llvm/lib/CodeGen/IntrinsicLowering.cpp:1.26
--- llvm/lib/CodeGen/IntrinsicLowering.cpp:1.25 Mon Mar 28 14:05:49 2005
+++ llvm/lib/CodeGen/IntrinsicLowering.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- IntrinsicLowering.cpp - Intrinsic Lowering default implementation -===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the default intrinsic lowering implementation.
@@ -117,7 +117,7 @@
void DefaultIntrinsicLowering::LowerIntrinsicCall(CallInst *CI) {
Function *Callee = CI->getCalledFunction();
assert(Callee && "Cannot lower an indirect call!");
-
+
switch (Callee->getIntrinsicID()) {
case Intrinsic::not_intrinsic:
std::cerr << "Cannot lower a call to a non-intrinsic function '"
@@ -140,7 +140,7 @@
CI->replaceAllUsesWith(V);
break;
}
- case Intrinsic::sigsetjmp:
+ case Intrinsic::sigsetjmp:
if (CI->getType() != Type::VoidTy)
CI->replaceAllUsesWith(Constant::getNullValue(CI->getType()));
break;
@@ -163,7 +163,7 @@
case Intrinsic::returnaddress:
case Intrinsic::frameaddress:
std::cerr << "WARNING: this target does not support the llvm."
- << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
+ << (Callee->getIntrinsicID() == Intrinsic::returnaddress ?
"return" : "frame") << "address intrinsic.\n";
CI->replaceAllUsesWith(ConstantPointerNull::get(
cast<PointerType>(CI->getType())));
@@ -220,7 +220,7 @@
break;
}
}
-
+
assert(CI->use_empty() &&
"Lowering should have eliminated any uses of the intrinsic call!");
CI->getParent()->getInstList().erase(CI);
Index: llvm/lib/CodeGen/LiveIntervalAnalysis.cpp
diff -u llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.138 llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.139
--- llvm/lib/CodeGen/LiveIntervalAnalysis.cpp:1.138 Sat Apr 9 11:24:20 2005
+++ llvm/lib/CodeGen/LiveIntervalAnalysis.cpp Thu Apr 21 17:33:33 2005
@@ -742,7 +742,7 @@
// Get the register classes for the first reg.
if (MRegisterInfo::isPhysicalRegister(RegA)) {
- assert(MRegisterInfo::isVirtualRegister(RegB) &&
+ assert(MRegisterInfo::isVirtualRegister(RegB) &&
"Shouldn't consider two physregs!");
return !mf_->getSSARegMap()->getRegClass(RegB)->contains(RegA);
}
@@ -775,7 +775,7 @@
}
LiveInterval LiveIntervals::createInterval(unsigned reg) {
- float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
+ float Weight = MRegisterInfo::isPhysicalRegister(reg) ?
(float)HUGE_VAL :0.0F;
return LiveInterval(reg, Weight);
}
Index: llvm/lib/CodeGen/LiveInterval.cpp
diff -u llvm/lib/CodeGen/LiveInterval.cpp:1.19 llvm/lib/CodeGen/LiveInterval.cpp:1.20
--- llvm/lib/CodeGen/LiveInterval.cpp:1.19 Fri Dec 3 19:22:09 2004
+++ llvm/lib/CodeGen/LiveInterval.cpp Thu Apr 21 17:33:33 2005
@@ -34,7 +34,7 @@
//
bool LiveInterval::liveAt(unsigned I) const {
Ranges::const_iterator r = std::upper_bound(ranges.begin(), ranges.end(), I);
-
+
if (r == ranges.begin())
return false;
@@ -174,7 +174,7 @@
/// extendIntervalStartTo - This method is used when we want to extend the range
/// specified by I to start at the specified endpoint. To do this, we should
/// merge and eliminate all ranges that this will overlap with.
-LiveInterval::Ranges::iterator
+LiveInterval::Ranges::iterator
LiveInterval::extendIntervalStartTo(Ranges::iterator I, unsigned NewStart) {
assert(I != ranges.end() && "Not a valid interval!");
unsigned ValId = I->ValId;
Index: llvm/lib/CodeGen/LiveVariables.cpp
diff -u llvm/lib/CodeGen/LiveVariables.cpp:1.48 llvm/lib/CodeGen/LiveVariables.cpp:1.49
--- llvm/lib/CodeGen/LiveVariables.cpp:1.48 Sat Apr 9 10:23:25 2005
+++ llvm/lib/CodeGen/LiveVariables.cpp Thu Apr 21 17:33:33 2005
@@ -1,12 +1,12 @@
//===-- LiveVariables.cpp - Live Variable Analysis for Machine Code -------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This file implements the LiveVariable analysis pass. For each machine
// instruction in the function, this pass calculates the set of registers that
// are immediately dead after the instruction (i.e., the instruction calculates
@@ -98,7 +98,7 @@
assert(VRInfo.Kills[i]->getParent() != MBB && "entry should be at end!");
#endif
- assert(MBB != VRInfo.DefInst->getParent() &&
+ assert(MBB != VRInfo.DefInst->getParent() &&
"Should have kill for defblock!");
// Add a new kill entry for this basic block.
@@ -156,7 +156,7 @@
// physical register. This is a purely local property, because all physical
// register references as presumed dead across basic blocks.
//
- PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
+ PhysRegInfo = (MachineInstr**)alloca(sizeof(MachineInstr*) *
RegInfo->getNumRegs());
PhysRegUsed = (bool*)alloca(sizeof(bool)*RegInfo->getNumRegs());
std::fill(PhysRegInfo, PhysRegInfo+RegInfo->getNumRegs(), (MachineInstr*)0);
@@ -171,7 +171,7 @@
"Cannot have a live-in virtual register!");
HandlePhysRegDef(*I, 0);
}
-
+
// Calculate live variable information in depth first order on the CFG of the
// function. This guarantees that we will see the definition of a virtual
// register before its uses due to dominance properties of SSA (except for PHI
@@ -195,7 +195,7 @@
// Unless it is a PHI node. In this case, ONLY process the DEF, not any
// of the uses. They will be handled in other basic blocks.
- if (MI->getOpcode() == TargetInstrInfo::PHI)
+ if (MI->getOpcode() == TargetInstrInfo::PHI)
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
@@ -247,7 +247,7 @@
for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
E = MBB->succ_end(); SI != E; ++SI) {
MachineBasicBlock *Succ = *SI;
-
+
// PHI nodes are guaranteed to be at the top of the block...
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->getOpcode() == TargetInstrInfo::PHI; ++MI) {
@@ -267,7 +267,7 @@
}
}
}
-
+
// Finally, if the last block in the function is a return, make sure to mark
// it as using all of the live-out values in the function.
if (!MBB->empty() && TII.isReturn(MBB->back().getOpcode())) {
@@ -305,7 +305,7 @@
// function. If so, it is due to a bug in the instruction selector or some
// other part of the code generator if this happens.
#ifndef NDEBUG
- for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
+ for(MachineFunction::iterator i = MF.begin(), e = MF.end(); i != e; ++i)
assert(Visited.count(&*i) != 0 && "unreachable basic block found");
#endif
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
diff -u llvm/lib/CodeGen/MachineBasicBlock.cpp:1.24 llvm/lib/CodeGen/MachineBasicBlock.cpp:1.25
--- llvm/lib/CodeGen/MachineBasicBlock.cpp:1.24 Fri Apr 1 00:48:38 2005
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp Thu Apr 21 17:33:33 2005
@@ -133,7 +133,7 @@
}
void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
- std::vector<MachineBasicBlock *>::iterator I =
+ std::vector<MachineBasicBlock *>::iterator I =
std::find(Predecessors.begin(), Predecessors.end(), pred);
assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
Predecessors.erase(I);
Index: llvm/lib/CodeGen/MachineCodeEmitter.cpp
diff -u llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.22 llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.23
--- llvm/lib/CodeGen/MachineCodeEmitter.cpp:1.22 Mon Nov 22 15:54:26 2004
+++ llvm/lib/CodeGen/MachineCodeEmitter.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- MachineCodeEmitter.cpp - Implement the MachineCodeEmitter itf -----===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements the MachineCodeEmitter interface.
@@ -35,7 +35,7 @@
std::cout << "\n--- End of stub for Function\n";
return 0;
}
-
+
void emitByte(unsigned char B) {
std::cout << "0x" << std::hex << (unsigned int)B << std::dec << " ";
}
@@ -62,14 +62,14 @@
MachineCodeEmitter &MCE;
unsigned counter;
unsigned values[4];
-
+
public:
FilePrinterEmitter(MachineCodeEmitter &M, std::ostream &os)
: o(os), MCE(M), counter(0) {
openActual();
}
-
- ~FilePrinterEmitter() {
+
+ ~FilePrinterEmitter() {
o << "\n";
actual.close();
}
@@ -101,7 +101,7 @@
void *finishFunctionStub(const Function *F) {
return MCE.finishFunctionStub(F);
}
-
+
void emitByte(unsigned char B) {
MCE.emitByte(B);
actual << B; actual.flush();
Index: llvm/lib/CodeGen/MachineFunction.cpp
diff -u llvm/lib/CodeGen/MachineFunction.cpp:1.77 llvm/lib/CodeGen/MachineFunction.cpp:1.78
--- llvm/lib/CodeGen/MachineFunction.cpp:1.77 Sat Jan 29 18:09:23 2005
+++ llvm/lib/CodeGen/MachineFunction.cpp Thu Apr 21 17:33:33 2005
@@ -256,7 +256,7 @@
/// CreateStackObject - Create a stack object for a value of the specified type.
///
int MachineFrameInfo::CreateStackObject(const Type *Ty, const TargetData &TD) {
- return CreateStackObject((unsigned)TD.getTypeSize(Ty),
+ return CreateStackObject((unsigned)TD.getTypeSize(Ty),
TD.getTypeAlignment(Ty));
}
Index: llvm/lib/CodeGen/MachineInstr.cpp
diff -u llvm/lib/CodeGen/MachineInstr.cpp:1.106 llvm/lib/CodeGen/MachineInstr.cpp:1.107
--- llvm/lib/CodeGen/MachineInstr.cpp:1.106 Thu Oct 14 23:38:41 2004
+++ llvm/lib/CodeGen/MachineInstr.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- MachineInstr.cpp --------------------------------------------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// Methods common to all machine instructions.
@@ -28,7 +28,7 @@
// Global variable holding an array of descriptors for machine instructions.
// The actual object needs to be created separately for each target machine.
// This variable is initialized and reset by class TargetInstrInfo.
-//
+//
// FIXME: This should be a property of the target so that more than one target
// at a time can be active...
//
@@ -112,7 +112,7 @@
/// replace - Support for replacing opcode and operands of a MachineInstr in
/// place. This only resets the size of the operand vector and initializes it.
/// The new operands must be set explicitly later.
-///
+///
void MachineInstr::replace(short opcode, unsigned numOperands) {
assert(getNumImplicitRefs() == 0 &&
"This is probably broken because implicit refs are going to be lost.");
@@ -178,7 +178,7 @@
{
assert((!defsOnly || !notDefsAndUses) &&
"notDefsAndUses is irrelevant if defsOnly == true.");
-
+
unsigned numSubst = 0;
// Substitute operands
@@ -236,7 +236,7 @@
static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine *TM) {
const MRegisterInfo *MRI = 0;
-
+
if (TM) MRI = TM->getRegisterInfo();
bool CloseParen = true;
@@ -250,7 +250,7 @@
OS << "%hm(";
else
CloseParen = false;
-
+
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.getVRegValue()) {
@@ -333,21 +333,21 @@
// be attached to a Machine function yet
if (TM)
OS << TM->getInstrInfo()->getName(getOpcode());
-
+
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i);
if (i != StartOp)
OS << ",";
OS << " ";
::print(mop, OS, TM);
-
+
if (mop.isDef())
if (mop.isUse())
OS << "<def&use>";
else
OS << "<def>";
}
-
+
// code for printing implicit references
if (getNumImplicitRefs()) {
OS << "\tImplicitRefs: ";
@@ -361,7 +361,7 @@
OS << "<def>";
}
}
-
+
OS << "\n";
}
@@ -381,7 +381,7 @@
// Otherwise, print it out in the "raw" format without symbolic register names
// and such.
os << TargetInstrDescriptors[MI.getOpcode()].Name;
-
+
for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
os << "\t" << MI.getOperand(i);
if (MI.getOperand(i).isDef())
@@ -390,13 +390,13 @@
else
os << "<d>";
}
-
+
// code for printing implicit references
unsigned NumOfImpRefs = MI.getNumImplicitRefs();
if (NumOfImpRefs > 0) {
os << "\tImplicit: ";
for (unsigned z = 0; z < NumOfImpRefs; z++) {
- OutputValue(os, MI.getImplicitRef(z));
+ OutputValue(os, MI.getImplicitRef(z));
if (MI.getImplicitOp(z).isDef())
if (MI.getImplicitOp(z).isUse())
os << "<d&u>";
@@ -405,7 +405,7 @@
os << "\t";
}
}
-
+
return os << "\n";
}
@@ -418,7 +418,7 @@
OS << "%hh(";
else if (MO.isLoBits64())
OS << "%hm(";
-
+
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
if (MO.hasAllocatedReg())
@@ -479,10 +479,10 @@
assert(0 && "Unrecognized operand type");
break;
}
-
+
if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
OS << ")";
-
+
return OS;
}
Index: llvm/lib/CodeGen/Passes.cpp
diff -u llvm/lib/CodeGen/Passes.cpp:1.14 llvm/lib/CodeGen/Passes.cpp:1.15
--- llvm/lib/CodeGen/Passes.cpp:1.14 Wed Sep 1 17:55:35 2004
+++ llvm/lib/CodeGen/Passes.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- Passes.cpp - Target independent code generation passes ------------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file defines interfaces to access the target independent code
Index: llvm/lib/CodeGen/PHIElimination.cpp
diff -u llvm/lib/CodeGen/PHIElimination.cpp:1.33 llvm/lib/CodeGen/PHIElimination.cpp:1.34
--- llvm/lib/CodeGen/PHIElimination.cpp:1.33 Wed Sep 1 17:55:35 2004
+++ llvm/lib/CodeGen/PHIElimination.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- PhiElimination.cpp - Eliminate PHI nodes by inserting copies ------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass eliminates machine instruction PHI nodes by inserting copy
@@ -97,12 +97,12 @@
while (MBB.front().getOpcode() == TargetInstrInfo::PHI) {
// Unlink the PHI node from the basic block, but don't delete the PHI yet.
MachineInstr *MPhi = MBB.remove(MBB.begin());
-
+
assert(MRegisterInfo::isVirtualRegister(MPhi->getOperand(0).getReg()) &&
"PHI node doesn't write virt reg?");
unsigned DestReg = MPhi->getOperand(0).getReg();
-
+
// Create a new register for the incoming PHI arguments
const TargetRegisterClass *RC = MF.getSSARegMap()->getRegClass(DestReg);
unsigned IncomingReg = MF.getSSARegMap()->createVirtualRegister(RC);
@@ -112,7 +112,7 @@
// into the phi node destination.
//
RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC);
-
+
// Update live variable information if there is any...
if (LV) {
MachineInstr *PHICopy = prior(AfterPHIsIt);
@@ -128,7 +128,7 @@
// of any registers, or if the value itself is dead, we need to move this
// information over to the new copy we just inserted.
//
- std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator>
+ std::pair<LiveVariables::killed_iterator, LiveVariables::killed_iterator>
RKs = LV->killed_range(MPhi);
std::vector<std::pair<MachineInstr*, unsigned> > Range;
if (RKs.first != RKs.second) // Delete the range.
@@ -154,13 +154,13 @@
//
for (int i = MPhi->getNumOperands() - 1; i >= 2; i-=2) {
MachineOperand &opVal = MPhi->getOperand(i-1);
-
+
// Get the MachineBasicBlock equivalent of the BasicBlock that is the
// source path the PHI.
MachineBasicBlock &opBlock = *MPhi->getOperand(i).getMachineBasicBlock();
MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
-
+
// Check to make sure we haven't already emitted the copy for this block.
// This can happen because PHI nodes may have multiple entries for the
// same basic block. It doesn't matter which entry we use though, because
@@ -171,7 +171,7 @@
// register we are interested in!
//
bool HaveNotEmitted = true;
-
+
if (I != opBlock.begin()) {
MachineBasicBlock::iterator PrevInst = prior(I);
for (unsigned i = 0, e = PrevInst->getNumOperands(); i != e; ++i) {
@@ -180,7 +180,7 @@
if (MO.isDef()) {
HaveNotEmitted = false;
break;
- }
+ }
}
}
@@ -215,7 +215,7 @@
for (MachineBasicBlock::succ_iterator SI = opBlock.succ_begin(),
E = opBlock.succ_end(); SI != E && !ValueIsLive; ++SI) {
MachineBasicBlock *SuccMBB = *SI;
-
+
// Is it alive in this successor?
unsigned SuccIdx = SuccMBB->getNumber();
if (SuccIdx < InRegVI.AliveBlocks.size() &&
@@ -223,7 +223,7 @@
ValueIsLive = true;
break;
}
-
+
// Is it killed in this successor?
for (unsigned i = 0, e = InRegVI.Kills.size(); i != e; ++i)
if (InRegVI.Kills[i]->getParent() == SuccMBB) {
@@ -235,7 +235,7 @@
if (!ValueIsLive)
ValueIsLive = VRegPHIUseCount[SrcReg] != 0;
}
-
+
// Okay, if we now know that the value is not live out of the block,
// we can add a kill marker to the copy we inserted saying that it
// kills the incoming value!
@@ -252,7 +252,7 @@
}
}
}
-
+
// Really delete the PHI instruction now!
delete MPhi;
}
Index: llvm/lib/CodeGen/PrologEpilogInserter.cpp
diff -u llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.41 llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.42
--- llvm/lib/CodeGen/PrologEpilogInserter.cpp:1.41 Sun Jan 23 17:13:12 2005
+++ llvm/lib/CodeGen/PrologEpilogInserter.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- PrologEpilogInserter.cpp - Insert Prolog/Epilog code in function --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This pass is responsible for finalizing the functions frame layout, saving
@@ -190,7 +190,7 @@
void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
// Early exit if no caller saved registers are modified!
if (RegsToSave.empty())
- return;
+ return;
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
@@ -226,10 +226,10 @@
///
void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo();
-
+
bool StackGrowsDown =
TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown;
-
+
// Loop over all of the stack objects, assigning sequential addresses...
MachineFrameInfo *FFI = Fn.getFrameInfo();
@@ -241,12 +241,12 @@
int Offset = TFI.getOffsetOfLocalArea();
if (StackGrowsDown)
Offset = -Offset;
- assert(Offset >= 0
+ assert(Offset >= 0
&& "Local area offset should be in direction of stack growth");
// If there are fixed sized objects that are preallocated in the local area,
// non-fixed objects can't be allocated right at the start of local area.
- // We currently don't support filling in holes in between fixed sized objects,
+ // We currently don't support filling in holes in between fixed sized objects,
// so we adjust 'Offset' to point to the end of last fixed sized
// preallocated object.
for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
@@ -257,11 +257,11 @@
// the offset is negative, so we negate the offset to get the distance.
FixedOff = -FFI->getObjectOffset(i);
} else {
- // The maximum distance from the start pointer is at the upper
+ // The maximum distance from the start pointer is at the upper
// address of the object.
FixedOff = FFI->getObjectOffset(i) + FFI->getObjectSize(i);
- }
- if (FixedOff > Offset) Offset = FixedOff;
+ }
+ if (FixedOff > Offset) Offset = FixedOff;
}
for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
@@ -274,11 +274,11 @@
assert(Align <= StackAlignment && "Cannot align stack object to higher "
"alignment boundary than the stack itself!");
Offset = (Offset+Align-1)/Align*Align; // Adjust to Alignment boundary...
-
+
if (StackGrowsDown) {
FFI->setObjectOffset(i, -Offset); // Set the computed offset
} else {
- FFI->setObjectOffset(i, Offset);
+ FFI->setObjectOffset(i, Offset);
Offset += FFI->getObjectSize(i);
}
}
Index: llvm/lib/CodeGen/RegAllocLinearScan.cpp
diff -u llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.107 llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.108
--- llvm/lib/CodeGen/RegAllocLinearScan.cpp:1.107 Sun Jan 23 16:45:12 2005
+++ llvm/lib/CodeGen/RegAllocLinearScan.cpp Thu Apr 21 17:33:33 2005
@@ -208,7 +208,7 @@
assert(MRegisterInfo::isVirtualRegister(cur->reg) &&
"Can only allocate virtual registers!");
-
+
// Allocating a virtual register. try to find a free
// physical register or spill an interval (possibly this one) in order to
// assign it one.
@@ -266,7 +266,7 @@
active_[i] = active_.back();
active_.pop_back();
--i; --e;
-
+
} else if (IntervalPos->start > CurPoint) {
// Move inactive intervals to inactive list.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " inactive\n");
@@ -300,7 +300,7 @@
unsigned reg = Interval->reg;
IntervalPos = Interval->advanceTo(IntervalPos, CurPoint);
-
+
if (IntervalPos == Interval->end()) { // remove expired intervals.
DEBUG(std::cerr << "\t\tinterval " << *Interval << " expired\n");
@@ -331,7 +331,7 @@
/// updateSpillWeights - updates the spill weights of the specifed physical
/// register and its weight.
-static void updateSpillWeights(std::vector<float> &Weights,
+static void updateSpillWeights(std::vector<float> &Weights,
unsigned reg, float weight,
const MRegisterInfo *MRI) {
Weights[reg] += weight;
Index: llvm/lib/CodeGen/RegAllocLocal.cpp
diff -u llvm/lib/CodeGen/RegAllocLocal.cpp:1.71 llvm/lib/CodeGen/RegAllocLocal.cpp:1.72
--- llvm/lib/CodeGen/RegAllocLocal.cpp:1.71 Sun Jan 23 16:51:56 2005
+++ llvm/lib/CodeGen/RegAllocLocal.cpp Thu Apr 21 17:33:33 2005
@@ -210,7 +210,7 @@
///
MachineInstr *reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
unsigned OpNum);
-
+
void reloadPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
unsigned PhysReg);
Index: llvm/lib/CodeGen/RegAllocSimple.cpp
diff -u llvm/lib/CodeGen/RegAllocSimple.cpp:1.62 llvm/lib/CodeGen/RegAllocSimple.cpp:1.63
--- llvm/lib/CodeGen/RegAllocSimple.cpp:1.62 Sun Jan 23 16:55:45 2005
+++ llvm/lib/CodeGen/RegAllocSimple.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- RegAllocSimple.cpp - A simple generic register allocator ----------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements a simple register allocator. *Very* simple: It immediate
@@ -36,7 +36,7 @@
const TargetMachine *TM;
const MRegisterInfo *RegInfo;
bool *PhysRegsEverUsed;
-
+
// StackSlotForVirtReg - Maps SSA Regs => frame index on the stack where
// these values are spilled
std::map<unsigned, int> StackSlotForVirtReg;
@@ -102,7 +102,7 @@
// Allocate a new stack object for this spill location...
int FrameIdx = MF->getFrameInfo()->CreateStackObject(RC->getSize(),
RC->getAlignment());
-
+
// Assign the slot...
StackSlotForVirtReg.insert(I, std::make_pair(VirtReg, FrameIdx));
@@ -115,10 +115,10 @@
TargetRegisterClass::iterator RE = RC->allocation_order_end(*MF);
while (1) {
- unsigned regIdx = RegClassIdx[RC]++;
+ unsigned regIdx = RegClassIdx[RC]++;
assert(RI+regIdx != RE && "Not enough registers!");
unsigned PhysReg = *(RI+regIdx);
-
+
if (!RegsUsed[PhysReg]) {
PhysRegsEverUsed[PhysReg] = true;
return PhysReg;
@@ -158,7 +158,7 @@
std::map<unsigned, unsigned> Virt2PhysRegMap;
RegsUsed.resize(RegInfo->getNumRegs());
-
+
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
unsigned Opcode = MI->getOpcode();
@@ -166,23 +166,23 @@
const unsigned *Regs;
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
RegsUsed[*Regs] = true;
-
+
for (Regs = Desc.ImplicitDefs; *Regs; ++Regs) {
RegsUsed[*Regs] = true;
PhysRegsEverUsed[*Regs] = true;
}
-
+
// Loop over uses, move from memory into registers.
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &op = MI->getOperand(i);
-
+
if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, TM));
-
+
// make sure the same virtual register maps to the same physical
// register in any given instruction
unsigned physReg = Virt2PhysRegMap[virtualReg];
@@ -211,7 +211,7 @@
}
}
MI->SetMachineOperandReg(i, physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
+ DEBUG(std::cerr << "virt: " << virtualReg <<
", phys: " << op.getReg() << "\n");
}
}
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
diff -u llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.29 llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.30
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp:1.29 Wed Jan 19 01:08:42 2005
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp Thu Apr 21 17:33:33 2005
@@ -57,7 +57,7 @@
bool runOnMachineFunction(MachineFunction&);
};
- RegisterPass<TwoAddressInstructionPass>
+ RegisterPass<TwoAddressInstructionPass>
X("twoaddressinstruction", "Two-Address instruction pass");
};
@@ -152,7 +152,7 @@
mbbi->insert(mi, NewMI); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst.
mi = NewMI;
- }
+ }
++NumCommuted;
regB = regC;
@@ -161,7 +161,7 @@
}
}
// If this instruction is potentially convertible to a true
- // three-address instruction,
+ // three-address instruction,
if (TID.Flags & M_CONVERTIBLE_TO_3_ADDR)
if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
@@ -197,7 +197,7 @@
// replace all occurences of regB with regA
for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
- if (mi->getOperand(i).isRegister() &&
+ if (mi->getOperand(i).isRegister() &&
mi->getOperand(i).getReg() == regB)
mi->SetMachineOperandReg(i, regA);
}
Index: llvm/lib/CodeGen/UnreachableBlockElim.cpp
diff -u llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.5 llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.6
--- llvm/lib/CodeGen/UnreachableBlockElim.cpp:1.5 Thu Mar 17 09:36:37 2005
+++ llvm/lib/CodeGen/UnreachableBlockElim.cpp Thu Apr 21 17:33:33 2005
@@ -1,12 +1,12 @@
//===-- UnreachableBlockElim.cpp - Remove unreachable blocks for codegen --===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
// This pass is an extremely simple version of the SimplifyCFG pass. Its sole
// job is to delete LLVM basic blocks that are not reachable from the entry
// node. To do this, it performs a simple depth first traversal of the CFG,
Index: llvm/lib/CodeGen/ValueTypes.cpp
diff -u llvm/lib/CodeGen/ValueTypes.cpp:1.2 llvm/lib/CodeGen/ValueTypes.cpp:1.3
--- llvm/lib/CodeGen/ValueTypes.cpp:1.2 Thu Jan 20 11:32:28 2005
+++ llvm/lib/CodeGen/ValueTypes.cpp Thu Apr 21 17:33:33 2005
@@ -1,10 +1,10 @@
//===-- ValueTypes.cpp - Implementation of MVT::ValueType methods ---------===//
-//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
//
// This file implements methods in the CodeGen/ValueTypes.h header.
Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.36 llvm/lib/CodeGen/VirtRegMap.cpp:1.37
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.36 Mon Apr 4 16:35:34 2005
+++ llvm/lib/CodeGen/VirtRegMap.cpp Thu Apr 21 17:33:33 2005
@@ -82,7 +82,7 @@
unsigned OpNo, MachineInstr *NewMI) {
// Move previous memory references folded to new instruction.
MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
- for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
+ for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
MI2VirtMap.erase(I++);
@@ -108,7 +108,7 @@
e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
-
+
}
for (unsigned i = MRegisterInfo::FirstVirtualRegister,
@@ -163,7 +163,7 @@
unsigned PhysReg = VRM.getPhys(VirtReg);
if (VRM.hasStackSlot(VirtReg)) {
int StackSlot = VRM.getStackSlot(VirtReg);
-
+
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
@@ -172,7 +172,7 @@
++NumLoads;
DEBUG(std::cerr << '\t' << *prior(MII));
}
-
+
if (MO.isDef()) {
MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
++NumStores;
@@ -255,16 +255,16 @@
struct ReusedOp {
// The MachineInstr operand that reused an available value.
unsigned Operand;
-
+
// StackSlot - The spill slot of the value being reused.
unsigned StackSlot;
-
+
// PhysRegReused - The physical register the value was available in.
unsigned PhysRegReused;
-
+
// AssignedPhysReg - The physreg that was assigned for use by the reload.
unsigned AssignedPhysReg;
-
+
ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr)
: Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr) {}
};
@@ -384,7 +384,7 @@
// Okay, we found out that an alias of a reused register
// was used. This isn't good because it means we have
// to undo a previous reuse.
- MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
+ MRI->loadRegFromStackSlot(MBB, &MI, Op.AssignedPhysReg,
Op.StackSlot);
ClobberPhysReg(Op.AssignedPhysReg, SpillSlotsAvailable,
PhysRegsAvailable);
@@ -510,12 +510,12 @@
break;
}
}
-
+
if (!OpTakenCareOf) {
ClobberPhysReg(VirtReg, SpillSlotsAvailable, PhysRegsAvailable);
TakenCareOf = true;
}
- }
+ }
if (!TakenCareOf) {
// The only vregs left are stack slot definitions.
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