[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.88 -> 1.89
---
Log message:

Fold (x & 8) != 0 and (x & 8) == 8  into (x & 8) >> 3.

This turns this PPC code:

        rlwinm r2, r3, 0, 28, 28
        cmpwi cr7, r2, 8
        mfcr r2
        rlwinm r3, r2, 31, 31, 31

into this:

        rlwinm r2, r3, 0, 28, 28
        srwi r2, r2, 3
        rlwinm r3, r2, 0, 31, 31

Next up, nuking the extra and.



---
Diffs of the changes:  (+22 -0)

 SelectionDAG.cpp |   22 ++++++++++++++++++++++
 1 files changed, 22 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.88 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.89
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.88	Sun Apr 17 23:48:12 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Thu Apr 21 01:12:41 2005
@@ -507,6 +507,28 @@
 
       // FIXME: Implement the rest of these.
 
+
+      // Fold bit comparisons when we can.
+      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
+          VT == N1.getValueType() && N1.getOpcode() == ISD::AND)
+        if (ConstantSDNode *AndRHS =
+                    dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+          if (Cond == ISD::SETNE && C2 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
+            // Perform the xform if the AND RHS is a single bit.
+            if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
+              return getNode(ISD::SRL, VT, N1,
+                             getConstant(ExactLog2(AndRHS->getValue()),
+                                                   TLI.getShiftAmountTy()));
+            }
+          } else if (Cond == ISD::SETEQ && C2 == AndRHS->getValue()) {
+            // (X & 8) == 8  -->  (X & 8) >> 3
+            // Perform the xform if C2 is a single bit.
+            if ((C2 & (C2-1)) == 0) {
+              return getNode(ISD::SRL, VT, N1,
+                             getConstant(ExactLog2(C2),TLI.getShiftAmountTy()));
+            }
+          }
+        }
     }
   } else if (isa<ConstantSDNode>(N1.Val)) {
       // Ensure that the constant occurs on the RHS.