[llvm-commits] CVS: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td PowerPCInstrInfo.td
Chris Lattner
lattner at cs.uiuc.edu
Mon Apr 18 21:51:46 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PowerPCInstrFormats.td updated: 1.37 -> 1.38
PowerPCInstrInfo.td updated: 1.67 -> 1.68
---
Log message:
Convert XLForm and XForm instructions over to use PPC64 when appropriate.
---
Diffs of the changes: (+117 -134)
PowerPCInstrFormats.td | 91 ++++++++++++---------------
PowerPCInstrInfo.td | 160 +++++++++++++++++++++++--------------------------
2 files changed, 117 insertions(+), 134 deletions(-)
Index: llvm/lib/Target/PowerPC/PowerPCInstrFormats.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.37 llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.38
--- llvm/lib/Target/PowerPC/PowerPCInstrFormats.td:1.37 Mon Apr 18 23:40:07 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrFormats.td Mon Apr 18 23:51:30 2005
@@ -200,9 +200,9 @@
: DSForm_1<opcode, xo, ppc64, vmx, OL, asmstr>;
// 1.7.6 X-Form
-class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
+class XForm_base_r3xo<bits<6> opcode, bits<10> xo, bit rc,
dag OL, string asmstr>
- : I<opcode, ppc64, vmx, OL, asmstr> {
+ : I<opcode, 0, 0, OL, asmstr> {
bits<5> RST;
bits<5> A;
bits<5> B;
@@ -217,9 +217,8 @@
// This is the same as XForm_base_r3xo, but the first two operands are swapped
// when code is emitted.
class XForm_base_r3xo_swapped
- <bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : I<opcode, ppc64, vmx, OL, asmstr> {
+ <bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
+ : I<opcode, 0, 0, OL, asmstr> {
bits<5> A;
bits<5> RST;
bits<5> B;
@@ -232,31 +231,26 @@
}
-class XForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
-
-class XForm_6<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr>;
-
-class XForm_8<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr>;
-
-class XForm_10<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
-}
-
-class XForm_11<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo_swapped<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
+class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
+
+class XForm_6<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
+ : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr>;
+
+class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : XForm_base_r3xo<opcode, xo, 0, OL, asmstr>;
+
+class XForm_10<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
+ : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
+}
+
+class XForm_11<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
+ : XForm_base_r3xo_swapped<opcode, xo, rc, OL, asmstr> {
let B = 0;
}
-class XForm_16<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : I<opcode, 0, 0, OL, asmstr> {
bits<3> BF;
bits<1> L;
bits<5> RA;
@@ -271,14 +265,13 @@
let Inst{31} = 0;
}
-class XForm_16_ext<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_16<opcode, xo, ppc64, vmx, OL, asmstr> {
- let L = ppc64;
+class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : XForm_16<opcode, xo, OL, asmstr> {
+ let L = PPC64;
}
-class XForm_17<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : I<opcode, 0, 0, OL, asmstr> {
bits<3> BF;
bits<5> FRA;
bits<5> FRB;
@@ -291,25 +284,22 @@
let Inst{31} = 0;
}
-class XForm_25<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
+class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
}
-class XForm_26<bits<6> opcode, bits<10> xo, bit rc, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, rc, ppc64, vmx, OL, asmstr> {
+class XForm_26<bits<6> opcode, bits<10> xo, bit rc, dag OL, string asmstr>
+ : XForm_base_r3xo<opcode, xo, rc, OL, asmstr> {
let A = 0;
}
-class XForm_28<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
+class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : XForm_base_r3xo<opcode, xo, 0, OL, asmstr> {
}
// 1.7.7 XL-Form
-class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : I<opcode, 0, 0, OL, asmstr> {
bits<3> CRD;
bits<2> CRDb;
bits<3> CRA;
@@ -327,8 +317,8 @@
let Inst{31} = 0;
}
-class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
- dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+class XLForm_2<bits<6> opcode, bits<10> xo, bit lk,
+ dag OL, string asmstr> : I<opcode, 0, 0, OL, asmstr> {
bits<5> BO;
bits<5> BI;
bits<2> BH;
@@ -342,16 +332,15 @@
}
class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo,
- bits<5> bi, bit lk, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XLForm_2<opcode, xo, lk, ppc64, vmx, OL, asmstr> {
+ bits<5> bi, bit lk, dag OL, string asmstr>
+ : XLForm_2<opcode, xo, lk, OL, asmstr> {
let BO = bo;
let BI = bi;
let BH = 0;
}
-class XLForm_3<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr>
+ : I<opcode, 0, 0, OL, asmstr> {
bits<3> BF;
bits<3> BFA;
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.67 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.68
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.67 Mon Apr 18 23:40:07 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Mon Apr 18 23:51:30 2005
@@ -20,8 +20,8 @@
let isTerminator = 1 in {
let isReturn = 1 in
- def BLR : XLForm_2_ext<19, 16, 20, 0, 0, 0, 0, (ops), "blr">;
- def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, 0, 0, (ops), "bctr">;
+ def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">;
+ def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">;
}
def u5imm : Operand<i8> {
@@ -94,7 +94,7 @@
CR0,CR1,CR5,CR6,CR7] in {
// Convenient aliases for call instructions
def CALLpcrel : IForm<18, 0, 1, 0, 0, (ops target:$func), "bl $func">;
- def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, 0, 0, (ops), "bctrl">;
+ def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, (ops), "bctrl">;
}
// D-Form instructions. Most instructions that perform an operation on a
@@ -214,155 +214,149 @@
// register and another register are of this type.
//
let isLoad = 1 in {
-def LBZX : XForm_1<31, 87, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"lbzx $dst, $base, $index">;
-def LHAX : XForm_1<31, 343, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"lhax $dst, $base, $index">;
-def LHZX : XForm_1<31, 279, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"lhzx $dst, $base, $index">;
-def LWAX : XForm_1<31, 341, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "lwax $dst, $base, $index">;
-def LWZX : XForm_1<31, 23, 0, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+ "lwax $dst, $base, $index">, isPPC64;
+def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
"lwzx $dst, $base, $index">;
-def LDX : XForm_1<31, 21, 1, 0, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
- "ldx $dst, $base, $index">;
+def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index),
+ "ldx $dst, $base, $index">, isPPC64;
}
-def AND : XForm_6<31, 28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def AND : XForm_6<31, 28, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB">;
let Defs = [CR0] in
-def ANDo : XForm_6<31, 28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def ANDo : XForm_6<31, 28, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and. $rA, $rS, $rB">;
-def ANDC : XForm_6<31, 60, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def ANDC : XForm_6<31, 60, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"andc $rA, $rS, $rB">;
-def EQV : XForm_6<31, 284, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def EQV : XForm_6<31, 284, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"eqv $rA, $rS, $rB">;
-def NAND : XForm_6<31, 476, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def NAND : XForm_6<31, 476, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nand $rA, $rS, $rB">;
-def NOR : XForm_6<31, 124, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def NOR : XForm_6<31, 124, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nor $rA, $rS, $rB">;
-def OR : XForm_6<31, 444, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def OR : XForm_6<31, 444, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"or $rA, $rS, $rB">;
let Defs = [CR0] in
-def ORo : XForm_6<31, 444, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def ORo : XForm_6<31, 444, 1, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"or. $rA, $rS, $rB">;
-def ORC : XForm_6<31, 412, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def ORC : XForm_6<31, 412, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"orc $rA, $rS, $rB">;
-def SLD : XForm_6<31, 27, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "sld $rA, $rS, $rB">;
-def SLW : XForm_6<31, 24, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def SLD : XForm_6<31, 27, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+ "sld $rA, $rS, $rB">, isPPC64;
+def SLW : XForm_6<31, 24, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"slw $rA, $rS, $rB">;
-def SRD : XForm_6<31, 539, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srd $rA, $rS, $rB">;
-def SRW : XForm_6<31, 536, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def SRD : XForm_6<31, 539, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+ "srd $rA, $rS, $rB">, isPPC64;
+def SRW : XForm_6<31, 536, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"srw $rA, $rS, $rB">;
-def SRAD : XForm_6<31, 794, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "srad $rA, $rS, $rB">;
-def SRAW : XForm_6<31, 792, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def SRAD : XForm_6<31, 794, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+ "srad $rA, $rS, $rB">, isPPC64;
+def SRAW : XForm_6<31, 792, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"sraw $rA, $rS, $rB">;
-def XOR : XForm_6<31, 316, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def XOR : XForm_6<31, 316, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"xor $rA, $rS, $rB">;
let isStore = 1 in {
-def STBX : XForm_8<31, 215, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+def STBX : XForm_8<31, 215, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stbx $rS, $rA, $rB">;
-def STHX : XForm_8<31, 407, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+def STHX : XForm_8<31, 407, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"sthx $rS, $rA, $rB">;
-def STWX : XForm_8<31, 151, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+def STWX : XForm_8<31, 151, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwx $rS, $rA, $rB">;
-def STWUX : XForm_8<31, 183, 0, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwux $rS, $rA, $rB">;
-def STDX : XForm_8<31, 149, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdx $rS, $rA, $rB">;
-def STDUX : XForm_8<31, 181, 1, 0, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
- "stdux $rS, $rA, $rB">;
+def STDX : XForm_8<31, 149, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stdx $rS, $rA, $rB">, isPPC64;
+def STDUX : XForm_8<31, 181, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
+ "stdux $rS, $rA, $rB">, isPPC64;
}
-def SRAWI : XForm_10<31, 824, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
+def SRAWI : XForm_10<31, 824, 0, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
"srawi $rA, $rS, $SH">;
-def CNTLZW : XForm_11<31, 26, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+def CNTLZW : XForm_11<31, 26, 0, (ops GPRC:$rA, GPRC:$rS),
"cntlzw $rA, $rS">;
-def EXTSB : XForm_11<31, 954, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+def EXTSB : XForm_11<31, 954, 0, (ops GPRC:$rA, GPRC:$rS),
"extsb $rA, $rS">;
-def EXTSH : XForm_11<31, 922, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS),
+def EXTSH : XForm_11<31, 922, 0, (ops GPRC:$rA, GPRC:$rS),
"extsh $rA, $rS">;
-def EXTSW : XForm_11<31, 986, 0, 1, 0, (ops GPRC:$rA, GPRC:$rS),
- "extsw $rA, $rS">;
-def CMP : XForm_16<31, 0, 0, 0,
- (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
+def EXTSW : XForm_11<31, 986, 0, (ops GPRC:$rA, GPRC:$rS),
+ "extsw $rA, $rS">, isPPC64;
+def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
"cmp $crD, $long, $rA, $rB">;
-def CMPL : XForm_16<31, 32, 0, 0,
- (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
+def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
"cmpl $crD, $long, $rA, $rB">;
-def CMPW : XForm_16_ext<31, 0, 0, 0,
- (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
"cmpw $crD, $rA, $rB">;
-def CMPD : XForm_16_ext<31, 0, 1, 0,
- (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpd $crD, $rA, $rB">;
-def CMPLW : XForm_16_ext<31, 32, 0, 0,
- (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+ "cmpd $crD, $rA, $rB">, isPPC64;
+def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
"cmplw $crD, $rA, $rB">;
-def CMPLD : XForm_16_ext<31, 32, 1, 0,
- (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
- "cmpld $crD, $rA, $rB">;
-def FCMPO : XForm_17<63, 32, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
+ "cmpld $crD, $rA, $rB">, isPPC64;
+def FCMPO : XForm_17<63, 32, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
"fcmpo $crD, $fA, $fB">;
-def FCMPU : XForm_17<63, 0, 0, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
+def FCMPU : XForm_17<63, 0, (ops CRRC:$crD, FPRC:$fA, FPRC:$fB),
"fcmpu $crD, $fA, $fB">;
let isLoad = 1 in {
-def LFSX : XForm_25<31, 535, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+def LFSX : XForm_25<31, 535, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
"lfsx $dst, $base, $index">;
-def LFDX : XForm_25<31, 599, 0, 0, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
+def LFDX : XForm_25<31, 599, (ops FPRC:$dst, GPRC:$base, GPRC:$index),
"lfdx $dst, $base, $index">;
}
-def FCFID : XForm_26<63, 846, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
- "fcfid $frD, $frB">;
-def FCTIDZ : XForm_26<63, 815, 0, 1, 0, (ops FPRC:$frD, FPRC:$frB),
- "fctidz $frD, $frB">;
-def FCTIWZ : XForm_26<63, 15, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FCFID : XForm_26<63, 846, 0, (ops FPRC:$frD, FPRC:$frB),
+ "fcfid $frD, $frB">, isPPC64;
+def FCTIDZ : XForm_26<63, 815, 0, (ops FPRC:$frD, FPRC:$frB),
+ "fctidz $frD, $frB">, isPPC64;
+def FCTIWZ : XForm_26<63, 15, 0, (ops FPRC:$frD, FPRC:$frB),
"fctiwz $frD, $frB">;
-def FABS : XForm_26<63, 264, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FABS : XForm_26<63, 264, 0, (ops FPRC:$frD, FPRC:$frB),
"fabs $frD, $frB">;
-def FMR : XForm_26<63, 72, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FMR : XForm_26<63, 72, 0, (ops FPRC:$frD, FPRC:$frB),
"fmr $frD, $frB">;
-def FNABS : XForm_26<63, 136, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FNABS : XForm_26<63, 136, 0, (ops FPRC:$frD, FPRC:$frB),
"fnabs $frD, $frB">;
-def FNEG : XForm_26<63, 40, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FNEG : XForm_26<63, 40, 0, (ops FPRC:$frD, FPRC:$frB),
"fneg $frD, $frB">;
-def FRSP : XForm_26<63, 12, 0, 0, 0, (ops FPRC:$frD, FPRC:$frB),
+def FRSP : XForm_26<63, 12, 0, (ops FPRC:$frD, FPRC:$frB),
"frsp $frD, $frB">;
let isStore = 1 in {
-def STFSX : XForm_28<31, 663, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+def STFSX : XForm_28<31, 663, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
"stfsx $frS, $rA, $rB">;
-def STFDX : XForm_28<31, 727, 0, 0, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
+def STFDX : XForm_28<31, 727, (ops FPRC:$frS, GPRC:$rA, GPRC:$rB),
"stfdx $frS, $rA, $rB">;
}
// XL-Form instructions. condition register logical ops.
//
-def CRAND : XLForm_1<19, 257, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRAND : XLForm_1<19, 257, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crand $Db, $Ab, $Bb">;
-def CRANDC : XLForm_1<19, 129, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRANDC : XLForm_1<19, 129, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crandc $Db, $Ab, $Bb">;
-def CREQV : XLForm_1<19, 289, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CREQV : XLForm_1<19, 289, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"creqv $Db, $Ab, $Bb">;
-def CRNAND : XLForm_1<19, 225, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRNAND : XLForm_1<19, 225, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crnand $Db, $Ab, $Bb">;
-def CRNOR : XLForm_1<19, 33, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRNOR : XLForm_1<19, 33, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crnor $Db, $Ab, $Bb">;
-def CROR : XLForm_1<19, 449, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CROR : XLForm_1<19, 449, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"cror $Db, $Ab, $Bb">;
-def CRORC : XLForm_1<19, 417, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRORC : XLForm_1<19, 417, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crorc $Db, $Ab, $Bb">;
-def CRXOR : XLForm_1<19, 193, 0, 0, (ops CRRC:$D, crbit:$Db,
+def CRXOR : XLForm_1<19, 193, (ops CRRC:$D, crbit:$Db,
CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
"crxor $Db, $Ab, $Bb">;
-def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
+def MCRF : XLForm_3<19, 0, (ops CRRC:$BF, CRRC:$BFA),
"mcrf $BF, $BFA">;
// XFX-Form instructions. Instructions that deal with SPRs
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