[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Chris Lattner
lattner at cs.uiuc.edu
Sun Apr 17 21:00:10 PDT 2005
Changes in directory llvm/lib/CodeGen/SelectionDAG:
SelectionDAG.cpp updated: 1.84 -> 1.85
---
Log message:
Fold:
// (X != 0) | (Y != 0) -> (X|Y != 0)
// (X == 0) & (Y == 0) -> (X|Y == 0)
Compiling this:
int %bar(int %a, int %b) {
entry:
%tmp.1 = setne int %a, 0
%tmp.2 = setne int %b, 0
%tmp.3 = or bool %tmp.1, %tmp.2
%retval = cast bool %tmp.3 to int
ret int %retval
}
to this:
_bar:
or r2, r3, r4
addic r3, r2, -1
subfe r3, r3, r2
blr
instead of:
_bar:
addic r2, r3, -1
subfe r2, r2, r3
addic r3, r4, -1
subfe r3, r3, r4
or r3, r2, r3
blr
---
Diffs of the changes: (+11 -0)
SelectionDAG.cpp | 11 +++++++++++
1 files changed, 11 insertions(+)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.84 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.85
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.84 Sun Apr 17 22:48:41 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Sun Apr 17 22:59:53 2005
@@ -933,6 +933,17 @@
SDOperand LR = LHS->getOperand(1), RR = RHS->getOperand(1);
ISD::CondCode Op2 = RHS->getCondition();
+ // (X != 0) | (Y != 0) -> (X|Y != 0)
+ // (X == 0) & (Y == 0) -> (X|Y == 0)
+ if (LR == RR && isa<ConstantSDNode>(LR) &&
+ cast<ConstantSDNode>(LR)->getValue() == 0 &&
+ Op2 == LHS->getCondition() && MVT::isInteger(LL.getValueType())) {
+ if ((Op2 == ISD::SETEQ && Opcode == ISD::AND) ||
+ (Op2 == ISD::SETNE && Opcode == ISD::OR))
+ return getSetCC(Op2, VT,
+ getNode(ISD::OR, LR.getValueType(), LL, RL), LR);
+ }
+
// (X op1 Y) | (Y op2 X) -> (X op1 Y) | (X swapop2 Y)
if (LL == RR && LR == RL) {
Op2 = ISD::getSetCCSwappedOperands(Op2);
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