[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PowerPC.h PowerPCTargetMachine.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.72 -> 1.73
PowerPC.h updated: 1.13 -> 1.14
PowerPCTargetMachine.cpp updated: 1.49 -> 1.50
---
Log message:

Make pattern isel default for ppc
Add new ppc beta option related to using condition registers
Make pattern isel control flag (-enable-pattern-isel) global and tristate
  0 == off
  1 == on
  2 == target default


---
Diffs of the changes:  (+24 -11)

 PPC32ISelPattern.cpp     |    5 ++---
 PowerPC.h                |    1 +
 PowerPCTargetMachine.cpp |   29 +++++++++++++++++++++--------
 3 files changed, 24 insertions(+), 11 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.72 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.73
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.72	Thu Apr 14 04:45:08 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Fri Apr 15 17:12:15 2005
@@ -1067,7 +1067,7 @@
       BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
     }
   } else {
-#if 0
+    if (PPCCRopts)
     if (CC.getOpcode() == ISD::AND || CC.getOpcode() == ISD::OR)
       if (CC.getOperand(0).Val->hasOneUse() &&
           CC.getOperand(1).Val->hasOneUse()) {
@@ -1093,7 +1093,6 @@
           return Result;
         }
     }
-#endif
     Opc = PPC::BNE;
     Tmp1 = SelectExpr(CC);
     BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
@@ -1127,7 +1126,7 @@
   unsigned Opc, CCReg;
   Select(N.getOperand(0));  //chain
   CCReg = SelectCC(N.getOperand(1), Opc);
-
+  
   // Iterate to the next basic block, unless we're already at the end of the
   ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
   if (++It == E) It = BB;


Index: llvm/lib/Target/PowerPC/PowerPC.h
diff -u llvm/lib/Target/PowerPC/PowerPC.h:1.13 llvm/lib/Target/PowerPC/PowerPC.h:1.14
--- llvm/lib/Target/PowerPC/PowerPC.h:1.13	Tue Apr  5 03:51:15 2005
+++ llvm/lib/Target/PowerPC/PowerPC.h	Fri Apr 15 17:12:15 2005
@@ -29,6 +29,7 @@
 FunctionPass *createDarwinAsmPrinter(std::ostream &OS, TargetMachine &TM);
 FunctionPass *createAIXAsmPrinter(std::ostream &OS, TargetMachine &TM);
 
+extern bool PPCCRopts;
 } // end namespace llvm;
 
 // GCC #defines PPC on Linux but we use it as our namespace name


Index: llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp
diff -u llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.49 llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.50
--- llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp:1.49	Tue Apr  5 03:51:15 2005
+++ llvm/lib/Target/PowerPC/PowerPCTargetMachine.cpp	Fri Apr 15 17:12:16 2005
@@ -30,15 +30,18 @@
 using namespace llvm;
 
 namespace llvm {
+  bool PPCCRopts;
   cl::opt<bool> AIX("aix", 
                     cl::desc("Generate AIX/xcoff instead of Darwin/MachO"), 
                     cl::Hidden);
-
   cl::opt<bool> EnablePPCLSR("enable-lsr-for-ppc", 
-                             cl::desc("Enable LSR for PPC (beta option!)"), 
+                             cl::desc("Enable LSR for PPC (beta)"), 
                              cl::Hidden);
-  cl::opt<bool> EnablePatternISel("enable-ppc-pattern-isel", cl::Hidden,
-                                cl::desc("Enable the pattern isel"));
+  cl::opt<bool, true> EnablePPCCRopts("enable-cc-opts", 
+                            cl::desc("Enable opts using condition regs (beta)"),
+                            cl::location(PPCCRopts),
+                            cl::init(false),
+                            cl::Hidden);
 }
 
 namespace {
@@ -96,12 +99,13 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
+  // Default to pattern ISel
   if (LP64)
     PM.add(createPPC64ISelPattern(*this));
-  else if (EnablePatternISel)
-    PM.add(createPPC32ISelPattern(*this));
-  else
+  else if (PatternISelTriState == 0)
     PM.add(createPPC32ISelSimple(*this));
+  else
+    PM.add(createPPC32ISelPattern(*this));
 
   if (PrintMachineCode)
     PM.add(createMachineFunctionPrinterPass(&std::cerr));
@@ -126,6 +130,8 @@
 }
 
 void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+  bool LP64 = (0 != dynamic_cast<PPC64TargetMachine *>(&TM));
+
   if (EnablePPCLSR) {
     PM.add(createLoopStrengthReducePass());
     PM.add(createCFGSimplificationPass());
@@ -145,7 +151,14 @@
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
-  PM.add(createPPC32ISelSimple(TM));
+  // Default to pattern ISel
+  if (LP64)
+    PM.add(createPPC64ISelPattern(TM));
+  else if (PatternISelTriState == 0)
+    PM.add(createPPC32ISelSimple(TM));
+  else
+    PM.add(createPPC32ISelPattern(TM));
+
   PM.add(createRegisterAllocator());
   PM.add(createPrologEpilogCodeInserter());