[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp

[Chris Lattner]

Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.19 -> 1.20
---
Log message:

Remove special handling of ZERO_EXTEND_INREG.  This pessimizes code, causing
things like this:

       mov r9 = 65535;;
       and r8 = r8, r9;;

To be emitted instead of:

        zxt2 r8 = r8;;

To get this back, the selector for ISD::AND should recognize this case.



---
Diffs of the changes:  (+0 -17)

 IA64ISelPattern.cpp |   17 -----------------
 1 files changed, 17 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.19 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.20
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.19	Tue Apr 12 09:54:44 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Tue Apr 12 21:41:52 2005
@@ -1304,23 +1304,6 @@
     return Result;
   }
 
-  case ISD::ZERO_EXTEND_INREG: {
-    Tmp1 = SelectExpr(N.getOperand(0));
-    MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);
-    switch(MVN->getExtraValueType())
-    {
-    default:
-      Node->dump();
-      assert(0 && "don't know how to zero extend this type");
-      break;
-    case MVT::i8: Opc = IA64::ZXT1; break;
-    case MVT::i16: Opc = IA64::ZXT2; break;
-    case MVT::i32: Opc = IA64::ZXT4; break;
-    }
-    BuildMI(BB, Opc, 1, Result).addReg(Tmp1);
-    return Result;
-  }
- 
   case ISD::SIGN_EXTEND_INREG: {
     Tmp1 = SelectExpr(N.getOperand(0));
     MVTSDNode* MVN = dyn_cast<MVTSDNode>(Node);