[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp IA64AsmPrinter.cpp IA64RegisterInfo.cpp IA64InstrInfo.td
Duraid Madina
duraid at octopus.com.au
Sun Apr 10 22:56:07 PDT 2005
Changes in directory llvm/lib/Target/IA64:
IA64ISelPattern.cpp updated: 1.15 -> 1.16
IA64AsmPrinter.cpp updated: 1.8 -> 1.9
IA64RegisterInfo.cpp updated: 1.2 -> 1.3
IA64InstrInfo.td updated: 1.8 -> 1.9
---
Log message:
assorted fixes:
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
* fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
* fix nasty thinko - didn't use two-address form of conditional add
for extending bools to integers, so occasionally there would be
garbage in the result. it's amazing how often zeros are just
sitting around in registers ;) - this should fix a bunch of tests.
---
Diffs of the changes: (+78 -66)
IA64AsmPrinter.cpp | 22 ++------------
IA64ISelPattern.cpp | 79 ++++++++++++++++++++++++++++++++++++---------------
IA64InstrInfo.td | 37 +++++++++--------------
IA64RegisterInfo.cpp | 6 +--
4 files changed, 78 insertions(+), 66 deletions(-)
Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.15 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.16
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.15 Fri Apr 8 22:22:24 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp Mon Apr 11 00:55:56 2005
@@ -639,28 +639,36 @@
else // false:
BuildMI(BB, IA64::CMPNE, 2, Result)
.addReg(IA64::r0).addReg(IA64::r0);
- return Result;
+ return Result; // early exit
}
- case MVT::i64: Opc = IA64::MOVLI32; break;
+ case MVT::i64: break;
}
int64_t immediate = cast<ConstantSDNode>(N)->getValue();
- if(immediate>>32) { // if our immediate really is big:
- int highPart = immediate>>32;
- int lowPart = immediate&0xFFFFFFFF;
- unsigned dummy = MakeReg(MVT::i64);
- unsigned dummy2 = MakeReg(MVT::i64);
- unsigned dummy3 = MakeReg(MVT::i64);
-
- BuildMI(BB, IA64::MOVLI32, 1, dummy).addImm(highPart);
- BuildMI(BB, IA64::SHLI, 2, dummy2).addReg(dummy).addImm(32);
- BuildMI(BB, IA64::MOVLI32, 1, dummy3).addImm(lowPart);
- BuildMI(BB, IA64::ADD, 2, Result).addReg(dummy2).addReg(dummy3);
- } else {
- BuildMI(BB, IA64::MOVLI32, 1, Result).addImm(immediate);
+
+ if(immediate==0) { // if the constant is just zero,
+ BuildMI(BB, IA64::MOV, 1, Result).addReg(IA64::r0); // just copy r0
+ return Result; // early exit
}
- return Result;
+ if (immediate <= 8191 && immediate >= -8192) {
+ // if this constants fits in 14 bits, we use a mov the assembler will
+ // turn into: "adds rDest=imm,r0" (and _not_ "andl"...)
+ BuildMI(BB, IA64::MOVSIMM14, 1, Result).addSImm(immediate);
+ return Result; // early exit
+ }
+
+ if (immediate <= 2097151 && immediate >= -2097152) {
+ // if this constants fits in 22 bits, we use a mov the assembler will
+ // turn into: "addl rDest=imm,r0"
+ BuildMI(BB, IA64::MOVSIMM22, 1, Result).addSImm(immediate);
+ return Result; // early exit
+ }
+
+ /* otherwise, our immediate is big, so we use movl */
+ uint64_t Imm = immediate;
+ BuildMI(BB, IA64::MOVLIMM64, 1, Result).addU64Imm(Imm);
+ return Result;
}
case ISD::UNDEF: {
@@ -706,7 +714,7 @@
// first load zero:
BuildMI(BB, IA64::MOV, 1, dummy).addReg(IA64::r0);
// ...then conditionally (PR:Tmp1) add 1:
- BuildMI(BB, IA64::CADDIMM22, 3, Result).addReg(dummy)
+ BuildMI(BB, IA64::TPCADDIMM22, 2, Result).addReg(dummy)
.addImm(1).addReg(Tmp1);
return Result; // XXX early exit!
}
@@ -823,15 +831,16 @@
return Result; // early exit
}
Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
if(DestType != MVT::f64) { // integer addition:
switch (ponderIntegerAdditionWith(N.getOperand(1), Tmp3)) {
case 1: // adding a constant that's 14 bits
BuildMI(BB, IA64::ADDIMM14, 2, Result).addReg(Tmp1).addSImm(Tmp3);
return Result; // early exit
} // fallthrough and emit a reg+reg ADD:
+ Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
} else { // this is a floating point addition
+ Tmp2 = SelectExpr(N.getOperand(1));
BuildMI(BB, IA64::FADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
@@ -868,7 +877,6 @@
BuildMI(BB, IA64::FMS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
return Result; // early exit
}
- Tmp1 = SelectExpr(N.getOperand(0));
Tmp2 = SelectExpr(N.getOperand(1));
if(DestType != MVT::f64) { // integer subtraction:
switch (ponderIntegerSubtractionFrom(N.getOperand(0), Tmp3)) {
@@ -876,8 +884,10 @@
BuildMI(BB, IA64::SUBIMM8, 2, Result).addSImm(Tmp3).addReg(Tmp2);
return Result; // early exit
} // fallthrough and emit a reg+reg SUB:
+ Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, IA64::SUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
} else { // this is a floating point subtraction
+ Tmp1 = SelectExpr(N.getOperand(0));
BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
}
return Result;
@@ -1311,9 +1321,20 @@
case ISD::SETCC: {
Tmp1 = SelectExpr(N.getOperand(0));
- Tmp2 = SelectExpr(N.getOperand(1));
+
if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
if (MVT::isInteger(SetCC->getOperand(0).getValueType())) {
+
+ if(ConstantSDNode *CSDN =
+ dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+ // if we are comparing against a constant zero
+ if(CSDN->getValue()==0)
+ Tmp2 = IA64::r0; // then we can just compare against r0
+ else
+ Tmp2 = SelectExpr(N.getOperand(1));
+ } else // not comparing against a constant
+ Tmp2 = SelectExpr(N.getOperand(1));
+
switch (SetCC->getCondition()) {
default: assert(0 && "Unknown integer comparison!");
case ISD::SETEQ:
@@ -1351,6 +1372,20 @@
else { // if not integer, should be FP. FIXME: what about bools? ;)
assert(SetCC->getOperand(0).getValueType() != MVT::f32 &&
"error: SETCC should have had incoming f32 promoted to f64!\n");
+
+ if(ConstantFPSDNode *CFPSDN =
+ dyn_cast<ConstantFPSDNode>(N.getOperand(1))) {
+
+ // if we are comparing against a constant +0.0 or +1.0
+ if(CFPSDN->isExactlyValue(+0.0))
+ Tmp2 = IA64::F0; // then we can just compare against f0
+ else if(CFPSDN->isExactlyValue(+1.0))
+ Tmp2 = IA64::F1; // or f1
+ else
+ Tmp2 = SelectExpr(N.getOperand(1));
+ } else // not comparing against a constant
+ Tmp2 = SelectExpr(N.getOperand(1));
+
switch (SetCC->getCondition()) {
default: assert(0 && "Unknown FP comparison!");
case ISD::SETEQ:
@@ -1836,7 +1871,7 @@
unsigned dummy3 = MakeReg(MVT::i64);
unsigned dummy4 = MakeReg(MVT::i64);
BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
- BuildMI(BB, IA64::CADDIMM22, 3, dummy4)
+ BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
.addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
BuildMI(BB, Opc, 2).addReg(dummy2).addReg(dummy4);
}
@@ -1858,7 +1893,7 @@
unsigned dummy3 = MakeReg(MVT::i64);
unsigned dummy4 = MakeReg(MVT::i64);
BuildMI(BB, IA64::MOV, 1, dummy3).addReg(IA64::r0);
- BuildMI(BB, IA64::CADDIMM22, 3, dummy4)
+ BuildMI(BB, IA64::TPCADDIMM22, 2, dummy4)
.addReg(dummy3).addImm(1).addReg(Tmp1); // if(Tmp1) dummy=0+1;
BuildMI(BB, Opc, 2).addReg(Tmp2).addReg(dummy4);
}
Index: llvm/lib/Target/IA64/IA64AsmPrinter.cpp
diff -u llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.8 llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.9
--- llvm/lib/Target/IA64/IA64AsmPrinter.cpp:1.8 Thu Apr 7 07:34:36 2005
+++ llvm/lib/Target/IA64/IA64AsmPrinter.cpp Mon Apr 11 00:55:56 2005
@@ -225,14 +225,6 @@
}
}
- void printS16ImmOperand(const MachineInstr *MI, unsigned OpNo,
- MVT::ValueType VT) {
- O << (short)MI->getOperand(OpNo).getImmedValue();
- }
- void printU16ImmOperand(const MachineInstr *MI, unsigned OpNo,
- MVT::ValueType VT) {
- O << (unsigned short)MI->getOperand(OpNo).getImmedValue();
- }
void printS8ImmOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
@@ -245,17 +237,11 @@
if(val>=8192) val=val-16384; // if negative, flip sign
O << val;
}
- void printS21ImmOperand(const MachineInstr *MI, unsigned OpNo,
- MVT::ValueType VT) {
- O << (int)MI->getOperand(OpNo).getImmedValue(); // FIXME (21, not 32!)
- }
- void printS32ImmOperand(const MachineInstr *MI, unsigned OpNo,
- MVT::ValueType VT) {
- O << (int)MI->getOperand(OpNo).getImmedValue();
- }
- void printU32ImmOperand(const MachineInstr *MI, unsigned OpNo,
+ void printS22ImmOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
- O << (unsigned int)MI->getOperand(OpNo).getImmedValue();
+ int val=(unsigned int)MI->getOperand(OpNo).getImmedValue();
+ if(val>=2097152) val=val-4194304; // if negative, flip sign
+ O << val;
}
void printU64ImmOperand(const MachineInstr *MI, unsigned OpNo,
MVT::ValueType VT) {
Index: llvm/lib/Target/IA64/IA64RegisterInfo.cpp
diff -u llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.2 llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.3
--- llvm/lib/Target/IA64/IA64RegisterInfo.cpp:1.2 Thu Mar 31 01:36:43 2005
+++ llvm/lib/Target/IA64/IA64RegisterInfo.cpp Mon Apr 11 00:55:56 2005
@@ -189,7 +189,7 @@
//fix up the old:
MI.SetMachineOperandReg(i, IA64::r22);
MachineInstr* nMI;
- nMI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(Offset);
+ nMI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(Offset);
MBB.insert(II, nMI);
nMI=BuildMI(IA64::ADD, 2, IA64::r22).addReg(BaseRegister)
.addReg(IA64::r22);
@@ -280,7 +280,7 @@
MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(-NumBytes);
MBB.insert(MBBI, MI);
} else { // we use r22 as a scratch register here
- MI=BuildMI(IA64::MOVLSI32, 1, IA64::r22).addSImm(-NumBytes);
+ MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addSImm(-NumBytes);
// FIXME: MOVLSI32 expects a _u_32imm
MBB.insert(MBBI, MI); // first load the decrement into r22
MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
@@ -328,7 +328,7 @@
MI=BuildMI(IA64::ADDIMM22, 2, IA64::r12).addReg(IA64::r12).addImm(NumBytes);
MBB.insert(MBBI, MI);
} else {
- MI=BuildMI(IA64::MOVLI32, 1, IA64::r22).addImm(NumBytes);
+ MI=BuildMI(IA64::MOVLIMM64, 1, IA64::r22).addImm(NumBytes);
MBB.insert(MBBI, MI);
MI=BuildMI(IA64::ADD, 2, IA64::r12).addReg(IA64::r12).addReg(IA64::r22);
MBB.insert(MBBI, MI);
Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.8 llvm/lib/Target/IA64/IA64InstrInfo.td:1.9
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.8 Fri Apr 8 05:01:48 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td Mon Apr 11 00:55:56 2005
@@ -22,15 +22,8 @@
def s14imm : Operand<i16> {
let PrintMethod = "printS14ImmOperand";
}
-def s16imm : Operand<i16>;
-def s21imm : Operand<i32> {
- let PrintMethod = "printS21ImmOperand";
-}
-def u32imm : Operand<i32> {
- let PrintMethod = "printU32ImmOperand";
-}
-def s32imm : Operand<i32> {
- let PrintMethod = "printS32ImmOperand";
+def s22imm : Operand<i32> {
+ let PrintMethod = "printS22ImmOperand";
}
def u64imm : Operand<i64> {
let PrintMethod = "printU64ImmOperand";
@@ -92,13 +85,11 @@
"($qp) cmp.eq $dst, p0 = $src3, $src4;;">;
}
-def MOVI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
+def MOVSIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, s14imm:$imm),
"mov $dst = $imm;;">;
-def MOVLI32 : AForm<0x03, 0x0b, (ops GR:$dst, u32imm:$imm),
- "movl $dst = $imm;;">;
-def MOVLSI32 : AForm<0x03, 0x0b, (ops GR:$dst, s32imm:$imm),
- "movl $dst = $imm;;">;
-def MOVLI64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
+def MOVSIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, s22imm:$imm),
+ "mov $dst = $imm;;">;
+def MOVLIMM64 : AForm<0x03, 0x0b, (ops GR:$dst, u64imm:$imm),
"movl $dst = $imm;;">;
def AND : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
@@ -109,15 +100,15 @@
"xor $dst = $src1, $src2;;">;
def SHL : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"shl $dst = $src1, $src2;;">;
-def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
- "shl $dst = $src1, $imm;;">; // FIXME: 6 immediate bits, not 21
+def SHLI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
+ "shl $dst = $src1, $imm;;">;
def SHRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"shr.u $dst = $src1, $src2;;">;
-def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
+def SHRUI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
"shr.u $dst = $src1, $imm;;">;
def SHRS : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, GR:$src2),
"shr $dst = $src1, $src2;;">;
-def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
+def SHRSI : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm),
"shr $dst = $src1, $imm;;">;
def EXTRU : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, u6imm:$imm1, u6imm:$imm2),
@@ -193,17 +184,17 @@
def ADDIMM14 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s14imm:$imm),
"adds $dst = $imm, $src1;;">;
-def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm),
+def ADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm),
"add $dst = $imm, $src1;;">;
-def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
+def CADDIMM22 : AForm<0x03, 0x0b, (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
"($qp) add $dst = $imm, $src1;;">;
let isTwoAddress = 1 in {
def TPCADDIMM22 : AForm<0x03, 0x0b,
- (ops GR:$dst, GR:$src1, s21imm:$imm, PR:$qp),
+ (ops GR:$dst, GR:$src1, s22imm:$imm, PR:$qp),
"($qp) add $dst = $imm, $dst;;">;
def TPCMPIMM8NE : AForm<0x03, 0x0b,
- (ops PR:$dst, PR:$src1, s21imm:$imm, GR:$src2, PR:$qp),
+ (ops PR:$dst, PR:$src1, s22imm:$imm, GR:$src2, PR:$qp),
"($qp) cmp.ne $dst , p0 = $imm, $src2;;">;
}
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