[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

SelectionDAG.cpp updated: 1.65 -> 1.66
---
Log message:

recognize some patterns as fabs operations, so that fabs at the source level
is deconstructed then reconstructed here.  This catches 19 fabs's in 177.mesa
9 in 168.wupwise, 5 in 171.swim, 3 in 172.mgrid, and 14 in 173.applu out of
specfp2000.

This allows the X86 code generator to make MUCH better code than before for
each of these and saves one instr on ppc.

This depends on the previous CFE patch to expose these correctly.


---
Diffs of the changes:  (+21 -0)

 SelectionDAG.cpp |   21 +++++++++++++++++++++
 1 files changed, 21 insertions(+)


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.65 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.66
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.65	Fri Apr  8 22:27:28 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Sat Apr  9 00:15:53 2005
@@ -952,6 +952,27 @@
       }
     }
 
+    // If this is a selectcc, check to see if we can simplify the result.
+    if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N1)) {
+      if (ConstantFPSDNode *CFP =
+          dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1)))
+        if (CFP->getValue() == 0.0) {   // Allow either -0.0 or 0.0
+          // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
+          if ((SetCC->getCondition() == ISD::SETGE ||
+               SetCC->getCondition() == ISD::SETGT) &&
+              N2 == SetCC->getOperand(0) && N3.getOpcode() == ISD::FNEG &&
+              N3.getOperand(0) == N2)
+            return getNode(ISD::FABS, VT, N2);
+
+          // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
+          if ((SetCC->getCondition() == ISD::SETLT ||
+               SetCC->getCondition() == ISD::SETLE) &&
+              N3 == SetCC->getOperand(0) && N2.getOpcode() == ISD::FNEG &&
+              N2.getOperand(0) == N3)
+            return getNode(ISD::FABS, VT, N3);
+        }
+
+    }
     break;
   case ISD::BRCOND:
     if (N2C)