[llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp

[Andrew Lenharth]

Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.81 -> 1.82
---
Log message:

fix copy/paste errors, and add imm support to SxADDQ and SxSUBQ

---
Diffs of the changes:  (+32 -8)

 AlphaISelPattern.cpp |   40 ++++++++++++++++++++++++++++++++--------
 1 files changed, 32 insertions(+), 8 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.81 llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.82
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.81	Wed Apr  6 15:25:34 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Wed Apr  6 15:59:59 2005
@@ -1703,34 +1703,58 @@
          N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
          cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 2)
       {
-        Tmp1 = SelectExpr(N.getOperand(1));
         Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
-        BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        if (N.getOperand(1).getOpcode() == ISD::Constant &&
+            cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
+          BuildMI(BB, isAdd?Alpha::S4ADDQi:Alpha::S4SUBQi, 2, Result).addReg(Tmp2)
+            .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
+        else {
+          Tmp1 = SelectExpr(N.getOperand(1));
+          BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S4SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        }
       }
       else if(N.getOperand(0).getOpcode() == ISD::SHL &&
          N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
          cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getValue() == 3)
       {
-        Tmp1 = SelectExpr(N.getOperand(1));
         Tmp2 = SelectExpr(N.getOperand(0).getOperand(0));
-        BuildMI(BB, isAdd?Alpha::S4ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        if (N.getOperand(1).getOpcode() == ISD::Constant &&
+            cast<ConstantSDNode>(N.getOperand(1))->getValue() <= 255)
+          BuildMI(BB, isAdd?Alpha::S8ADDQi:Alpha::S8SUBQi, 2, Result).addReg(Tmp2)
+            .addImm(cast<ConstantSDNode>(N.getOperand(1))->getValue());
+        else {
+          Tmp1 = SelectExpr(N.getOperand(1));
+          BuildMI(BB, isAdd?Alpha::S8ADDQ:Alpha::S8SUBQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        }
       }
       //Position prevents subs
       else if(N.getOperand(1).getOpcode() == ISD::SHL && isAdd &
          N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
          cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 2)
       {
-        Tmp1 = SelectExpr(N.getOperand(0));
         Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
-        BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        if (N.getOperand(0).getOpcode() == ISD::Constant &&
+            cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
+          BuildMI(BB, Alpha::S4ADDQi, 2, Result).addReg(Tmp2)
+            .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
+        else {
+          Tmp1 = SelectExpr(N.getOperand(0));
+          BuildMI(BB, Alpha::S4ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        }
       }
       else if(N.getOperand(0).getOpcode() == ISD::SHL && isAdd &&
          N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
          cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue() == 3)
       {
-        Tmp1 = SelectExpr(N.getOperand(0));
         Tmp2 = SelectExpr(N.getOperand(1).getOperand(0));
-        BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        if (N.getOperand(0).getOpcode() == ISD::Constant &&
+            cast<ConstantSDNode>(N.getOperand(0))->getValue() <= 255)
+          BuildMI(BB, Alpha::S8ADDQi, 2, Result).addReg(Tmp2)
+            .addImm(cast<ConstantSDNode>(N.getOperand(0))->getValue());
+        else {
+          Tmp1 = SelectExpr(N.getOperand(0));
+          BuildMI(BB, Alpha::S8ADDQ, 2, Result).addReg(Tmp2).addReg(Tmp1);
+        }
       }
       //small addi
       else if(N.getOperand(1).getOpcode() == ISD::Constant &&