[llvm-commits] CVS: llvm/lib/CodeGen/VirtRegMap.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen:

VirtRegMap.cpp updated: 1.35 -> 1.36
---
Log message:

Make sure to notice that explicit physregs are used in the function


---
Diffs of the changes:  (+29 -23)

 VirtRegMap.cpp |   52 +++++++++++++++++++++++++++++-----------------------
 1 files changed, 29 insertions(+), 23 deletions(-)


Index: llvm/lib/CodeGen/VirtRegMap.cpp
diff -u llvm/lib/CodeGen/VirtRegMap.cpp:1.35 llvm/lib/CodeGen/VirtRegMap.cpp:1.36
--- llvm/lib/CodeGen/VirtRegMap.cpp:1.35	Sun Jan 23 16:45:13 2005
+++ llvm/lib/CodeGen/VirtRegMap.cpp	Mon Apr  4 16:35:34 2005
@@ -157,31 +157,34 @@
       MachineInstr &MI = *MII;
       for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
         MachineOperand &MO = MI.getOperand(i);
-        if (MO.isRegister() && MO.getReg() &&
-            MRegisterInfo::isVirtualRegister(MO.getReg())) {
-          unsigned VirtReg = MO.getReg();
-          unsigned PhysReg = VRM.getPhys(VirtReg);
-          if (VRM.hasStackSlot(VirtReg)) {
-            int StackSlot = VRM.getStackSlot(VirtReg);
-
-            if (MO.isUse() &&
-                std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
-                           == LoadedRegs.end()) {
-              MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
-              LoadedRegs.push_back(VirtReg);
-              ++NumLoads;
-              DEBUG(std::cerr << '\t' << *prior(MII));
-            }
-
-            if (MO.isDef()) {
-              MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
-              ++NumStores;
+        if (MO.isRegister() && MO.getReg())
+          if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
+            unsigned VirtReg = MO.getReg();
+            unsigned PhysReg = VRM.getPhys(VirtReg);
+            if (VRM.hasStackSlot(VirtReg)) {
+              int StackSlot = VRM.getStackSlot(VirtReg);
+              
+              if (MO.isUse() &&
+                  std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
+                  == LoadedRegs.end()) {
+                MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot);
+                LoadedRegs.push_back(VirtReg);
+                ++NumLoads;
+                DEBUG(std::cerr << '\t' << *prior(MII));
+              }
+              
+              if (MO.isDef()) {
+                MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot);
+                ++NumStores;
+              }
             }
+            PhysRegsUsed[PhysReg] = true;
+            MI.SetMachineOperandReg(i, PhysReg);
+          } else {
+            PhysRegsUsed[MO.getReg()] = true;
           }
-          PhysRegsUsed[PhysReg] = true;
-          MI.SetMachineOperandReg(i, PhysReg);
-        }
       }
+
       DEBUG(std::cerr << '\t' << MI);
       LoadedRegs.clear();
     }
@@ -312,7 +315,10 @@
     for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
       MachineOperand &MO = MI.getOperand(i);
       if (MO.isRegister() && MO.getReg() &&
-          MRegisterInfo::isVirtualRegister(MO.getReg())) {
+          MRegisterInfo::isPhysicalRegister(MO.getReg()))
+        PhysRegsUsed[MO.getReg()] = true;
+      else if (MO.isRegister() && MO.getReg() &&
+               MRegisterInfo::isVirtualRegister(MO.getReg())) {
         unsigned VirtReg = MO.getReg();
 
         if (!VRM.hasStackSlot(VirtReg)) {