[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
Nate Begeman
natebegeman at mac.com
Sun Apr 3 23:52:49 PDT 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.39 -> 1.40
---
Log message:
Fix i64 return, fix CopyFromReg
---
Diffs of the changes: (+14 -3)
PPC32ISelPattern.cpp | 17 ++++++++++++++---
1 files changed, 14 insertions(+), 3 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.39 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.40
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.39 Sun Apr 3 18:11:17 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Mon Apr 4 01:52:38 2005
@@ -172,8 +172,13 @@
// We need to load the argument to a virtual register if we determined above
// that we ran out of physical registers of the appropriate type
if (needsLoad) {
+ unsigned SubregOffset = 0;
+ if (ObjectVT == MVT::i8) SubregOffset = 3;
+ if (ObjectVT == MVT::i16) SubregOffset = 2;
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
+ FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
+ DAG.getConstant(SubregOffset, MVT::i32));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
}
@@ -933,6 +938,9 @@
break;
}
+ if (ISD::CopyFromReg == opcode)
+ DestType = N.getValue(0).getValueType();
+
if (DestType == MVT::f64 || DestType == MVT::f32)
if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
return SelectExprFP(N, Result);
@@ -1109,9 +1117,12 @@
case MVT::i8:
case MVT::i16:
case MVT::i32:
- BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
- if (Node->getValueType(1) == MVT::i32)
- BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4).addReg(PPC::R4);
+ if (Node->getValueType(1) == MVT::i32) {
+ BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
+ BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
+ } else {
+ BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
+ }
break;
case MVT::f32:
case MVT::f64:
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