[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp IA64InstrInfo.td

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.8 -> 1.9
IA64InstrInfo.td updated: 1.2 -> 1.3
---
Log message:

add support FNEG and FABS



---
Diffs of the changes:  (+19 -5)

 IA64ISelPattern.cpp |   20 +++++++++++++++-----
 IA64InstrInfo.td    |    4 ++++
 2 files changed, 19 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.8 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.9
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.8	Fri Apr  1 23:03:21 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Fri Apr  1 23:18:38 2005
@@ -80,10 +80,6 @@
       setOperationAction(ISD::MEMSET           , MVT::Other, Expand);
       setOperationAction(ISD::MEMCPY           , MVT::Other, Expand);
 
-      // We don't support these yet.
-      setOperationAction(ISD::FNEG             , MVT::f64  , Expand);
-      setOperationAction(ISD::FABS             , MVT::f64  , Expand);
-      
       computeRegisterProperties();
 
       addLegalFPImmediate(+0.0);
@@ -794,7 +790,21 @@
       BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2);
     return Result;
   }
-		 
+
+  case ISD::FABS: {
+    Tmp1 = SelectExpr(N.getOperand(0));
+    assert(DestType == MVT::f64 && "trying to fabs something other than f64?");
+    BuildMI(BB, IA64::FABS, 1, Result).addReg(Tmp1);
+    return Result;
+  }
+ 
+  case ISD::FNEG: {
+    Tmp1 = SelectExpr(N.getOperand(0));
+    assert(DestType == MVT::f64 && "trying to fneg something other than f64?");
+    BuildMI(BB, IA64::FNEG, 1, Result).addReg(Tmp1);
+    return Result;
+  }
+      	 
   case ISD::AND: {
      switch (N.getValueType()) {
     default: assert(0 && "Cannot AND this type!");


Index: llvm/lib/Target/IA64/IA64InstrInfo.td
diff -u llvm/lib/Target/IA64/IA64InstrInfo.td:1.2 llvm/lib/Target/IA64/IA64InstrInfo.td:1.3
--- llvm/lib/Target/IA64/IA64InstrInfo.td:1.2	Thu Mar 31 01:32:32 2005
+++ llvm/lib/Target/IA64/IA64InstrInfo.td	Fri Apr  1 23:18:38 2005
@@ -227,6 +227,10 @@
   "fma $dst = $src1, $src2, $src3;;">;
 def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3),
   "fnma $dst = $src1, $src2, $src3;;">;
+def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+  "fabs $dst = $src;;">;
+def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src),
+  "fneg $dst = $src;;">;
 
 def CFMAS1 : AForm<0x03, 0x0b,
   (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),