[llvm-commits] CVS: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp SelectionDAG.cpp

[Chris Lattner]

Changes in directory llvm/lib/CodeGen/SelectionDAG:

LegalizeDAG.cpp updated: 1.68 -> 1.69
SelectionDAG.cpp updated: 1.56 -> 1.57
---
Log message:

fix some bugs in the implementation of SHL_PARTS and friends.


---
Diffs of the changes:  (+38 -11)

 LegalizeDAG.cpp  |   37 +++++++++++++++++++++++++++++--------
 SelectionDAG.cpp |   12 +++++++++---
 2 files changed, 38 insertions(+), 11 deletions(-)


Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.68 llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.69
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp:1.68	Fri Apr  1 21:38:53 2005
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp	Fri Apr  1 22:00:59 2005
@@ -125,7 +125,9 @@
                           SDOperand Source);
   bool ExpandShift(unsigned Opc, SDOperand Op, SDOperand Amt,
                    SDOperand &Lo, SDOperand &Hi);
-  void ExpandByParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
+  void ExpandShiftParts(unsigned NodeOp, SDOperand Op, SDOperand Amt,
+                        SDOperand &Lo, SDOperand &Hi);
+  void ExpandByParts(unsigned NodeOp, SDOperand LHS, SDOperand RHS,
                      SDOperand &Lo, SDOperand &Hi);
 
   SDOperand getIntPtrConstant(uint64_t Val) {
@@ -825,7 +827,10 @@
     break;
   }
   case ISD::ADD_PARTS:
-  case ISD::SUB_PARTS: {
+  case ISD::SUB_PARTS:
+  case ISD::SHL_PARTS:
+  case ISD::SRA_PARTS:
+  case ISD::SRL_PARTS: {
     std::vector<SDOperand> Ops;
     bool Changed = false;
     for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
@@ -1307,6 +1312,22 @@
   Hi = Lo.getValue(1);
 }
 
+void SelectionDAGLegalize::ExpandShiftParts(unsigned NodeOp,
+                                            SDOperand Op, SDOperand Amt,
+                                            SDOperand &Lo, SDOperand &Hi) {
+  // Expand the subcomponents.
+  SDOperand LHSL, LHSH;
+  ExpandOp(Op, LHSL, LHSH);
+
+  std::vector<SDOperand> Ops;
+  Ops.push_back(LHSL);
+  Ops.push_back(LHSH);
+  Ops.push_back(Amt);
+  Lo = DAG.getNode(NodeOp, LHSL.getValueType(), Ops);
+  Hi = Lo.getValue(1);
+}
+
+
 /// ExpandShift - Try to find a clever way to expand this shift operation out to
 /// smaller elements.  If we can't find a way that is more efficient than a
 /// libcall on this target, return false.  Otherwise, return true with the
@@ -1753,8 +1774,8 @@
 
     // If this target supports SHL_PARTS, use it.
     if (TLI.getOperationAction(ISD::SHL_PARTS, NVT) == TargetLowering::Legal) {
-      ExpandByParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
-                    Lo, Hi);
+      ExpandShiftParts(ISD::SHL_PARTS, Node->getOperand(0), Node->getOperand(1),
+                       Lo, Hi);
       break;
     }
 
@@ -1769,8 +1790,8 @@
 
     // If this target supports SRA_PARTS, use it.
     if (TLI.getOperationAction(ISD::SRA_PARTS, NVT) == TargetLowering::Legal) {
-      ExpandByParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
-                    Lo, Hi);
+      ExpandShiftParts(ISD::SRA_PARTS, Node->getOperand(0), Node->getOperand(1),
+                       Lo, Hi);
       break;
     }
 
@@ -1784,8 +1805,8 @@
 
     // If this target supports SRL_PARTS, use it.
     if (TLI.getOperationAction(ISD::SRL_PARTS, NVT) == TargetLowering::Legal) {
-      ExpandByParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
-                    Lo, Hi);
+      ExpandShiftParts(ISD::SRL_PARTS, Node->getOperand(0), Node->getOperand(1),
+                       Lo, Hi);
       break;
     }
 


Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
diff -u llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.56 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.57
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1.56	Fri Apr  1 21:30:42 2005
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp	Fri Apr  1 22:00:59 2005
@@ -907,6 +907,14 @@
   case ISD::DYNAMIC_STACKALLOC: // DYNAMIC_STACKALLOC produces pointer and chain
     N->setValueTypes(VT, MVT::Other);
     break;
+
+  case ISD::SRA_PARTS:
+  case ISD::SRL_PARTS:
+  case ISD::SHL_PARTS: {
+    std::vector<MVT::ValueType> V(N->getNumOperands()-1, VT);
+    N->setValueTypes(V);
+    break;
+  }
   }
 
   // FIXME: memoize NODES
@@ -924,9 +932,7 @@
   default:
     // FIXME: MEMOIZE!!
     SDNode *N = new SDNode(Opcode, Children);
-    if (Opcode != ISD::ADD_PARTS && Opcode != ISD::SUB_PARTS &&
-        Opcode != ISD::SRA_PARTS && Opcode != ISD::SRL_PARTS &&
-        Opcode != ISD::SHL_PARTS) {
+    if (Opcode != ISD::ADD_PARTS && Opcode != ISD::SUB_PARTS) {
       N->setValueTypes(VT);
     } else {
       std::vector<MVT::ValueType> V(N->getNumOperands()/2, VT);