[llvm-commits] CVS: llvm/lib/Target/IA64/IA64ISelPattern.cpp

[Duraid Madina]

Changes in directory llvm/lib/Target/IA64:

IA64ISelPattern.cpp updated: 1.6 -> 1.7
---
Log message:

repair mindless SELECT waste.



---
Diffs of the changes:  (+5 -15)

 IA64ISelPattern.cpp |   20 +++++---------------
 1 files changed, 5 insertions(+), 15 deletions(-)


Index: llvm/lib/Target/IA64/IA64ISelPattern.cpp
diff -u llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.6 llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.7
--- llvm/lib/Target/IA64/IA64ISelPattern.cpp:1.6	Thu Mar 31 06:31:11 2005
+++ llvm/lib/Target/IA64/IA64ISelPattern.cpp	Fri Apr  1 04:35:00 2005
@@ -554,11 +554,6 @@
       Tmp2 = SelectExpr(N.getOperand(1)); //Use if TRUE
       Tmp3 = SelectExpr(N.getOperand(2)); //Use if FALSE
 
-      // a temporary predicate register to hold the complement of the
-      // condition:
-      unsigned CondComplement=MakeReg(MVT::i1);
-      unsigned bogusTemp=MakeReg(MVT::i1);
-
       unsigned bogoResult;
       
       switch (N.getOperand(1).getValueType()) {
@@ -571,16 +566,11 @@
 	  bogoResult=MakeReg(MVT::f64);
 	  break;
       }
-      // set up the complement predicate reg (CondComplement = NOT Tmp1)
-      BuildMI(BB, IA64::CMPEQ, 2, bogusTemp).addReg(IA64::r0).addReg(IA64::r0);
-      BuildMI(BB, IA64::TPCMPNE, 3, CondComplement).addReg(bogusTemp)
-	.addReg(IA64::r0).addReg(IA64::r0).addReg(Tmp1);
-	
-      // and do a 'conditional move'
-      BuildMI(BB, IA64::PMOV, 2, bogoResult).addReg(Tmp2).addReg(Tmp1);
-      BuildMI(BB, IA64::CMOV, 2, Result).addReg(bogoResult).addReg(Tmp3)
-	.addReg(CondComplement);
- 
+
+      BuildMI(BB, IA64::MOV, 1, bogoResult).addReg(Tmp3);
+      BuildMI(BB, IA64::CMOV, 2, Result).addReg(bogoResult).addReg(Tmp2)
+	.addReg(Tmp1); // FIXME: should be FMOV/FCMOV sometimes,
+                       // though this will work for now (no JIT)
       return Result;
   }