[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp

[Nate Begeman]

Changes in directory llvm/lib/Target/PowerPC:

PPC32ISelPattern.cpp updated: 1.21 -> 1.22
---
Log message:

Pass the correct values to the chain argument for node construction during
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!


---
Diffs of the changes:  (+14 -6)

 PPC32ISelPattern.cpp |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)


Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.21 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.22
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.21	Wed Mar 30 18:15:26 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp	Wed Mar 30 20:05:53 2005
@@ -321,21 +321,22 @@
       case MVT::f64:
         if (FPR_remaining > 0) {
           if (isVarArg) {
-            MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                            Args[i].first, PtrOff));
+            SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
+                                          Args[i].first, PtrOff);
+            MemOps.push_back(Store);
             // Float varargs are always shadowed in available integer registers
             if (GPR_remaining > 0) {
-              SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
               MemOps.push_back(Load);
-              args_to_use.push_back(DAG.getCopyToReg(Chain, Load, 
+              args_to_use.push_back(DAG.getCopyToReg(Load, Load, 
                                                      GPR[GPR_idx]));
             }
             if (GPR_remaining > 1 && MVT::f64 == ArgVT) {
               SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
               PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
-              SDOperand Load = DAG.getLoad(MVT::i32, Chain, PtrOff);
+              SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
               MemOps.push_back(Load);
-              args_to_use.push_back(DAG.getCopyToReg(Chain, Load, 
+              args_to_use.push_back(DAG.getCopyToReg(Load, Load, 
                                                      GPR[GPR_idx+1]));
             }
           }
@@ -521,6 +522,13 @@
 //Check to see if the load is a constant offset from a base register
 void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
 {
+  unsigned imm = 0, opcode = N.getOpcode();
+  if (N.getOpcode() == ISD::ADD)
+    if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, imm)) {
+      Reg = SelectExpr(N.getOperand(0));
+      offset = imm;
+      return;
+    }
   Reg = SelectExpr(N);
   offset = 0;
   return;