[llvm-commits] CVS: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp PPC32ISelSimple.cpp PowerPCInstrInfo.td
Nate Begeman
natebegeman at mac.com
Mon Mar 28 14:28:48 PST 2005
Changes in directory llvm/lib/Target/PowerPC:
PPC32ISelPattern.cpp updated: 1.10 -> 1.11
PPC32ISelSimple.cpp updated: 1.129 -> 1.130
PowerPCInstrInfo.td updated: 1.50 -> 1.51
---
Log message:
Remove fake instruction 'subc' (mnemonic for subfc).
More pattern isel updates
---
Diffs of the changes: (+42 -12)
PPC32ISelPattern.cpp | 50 +++++++++++++++++++++++++++++++++++++++++---------
PPC32ISelSimple.cpp | 2 +-
PowerPCInstrInfo.td | 2 --
3 files changed, 42 insertions(+), 12 deletions(-)
Index: llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.10 llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.11
--- llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp:1.10 Mon Mar 28 13:36:43 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelPattern.cpp Mon Mar 28 16:28:37 2005
@@ -137,13 +137,22 @@
if (GPR_remaining > 1) {
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
+ SDOperand root = DAG.getRoot();
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ root, DAG.getConstant(1, MVT::i32));
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
+ root, DAG.getConstant(0, MVT::i32));
+
+ // Create the pair of virtual registers
MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
- unsigned virtReg =
- MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
- // FIXME: is this correct?
- argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
- argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
- // Push the arguments for emitting into BB later
+ unsigned virtReg = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
+
+ // Copy the extracted halves into the virtual registers
+ SDOperand argHi = DAG.getCopyFromReg(virtReg, MVT::i32, Hi);
+ SDOperand argLo = DAG.getCopyFromReg(virtReg+1, MVT::i32, Lo);
+
+ // Build the outgoing arg thingy
+ argt = newroot = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
argVR.push_back(virtReg); argVR.push_back(virtReg+1);
argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
@@ -592,6 +601,7 @@
}
case ISD::ConstantFP:
+ assert(0 && "ISD::ConstantFP Unimplemented");
abort();
case ISD::MUL:
@@ -688,14 +698,20 @@
return Result;
case ISD::ConstantPool:
- abort();
+ Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+ Tmp2 = MakeReg(MVT::i32);
+ BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
+ .addConstantPoolIndex(Tmp1);
+ BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
+ return Result;
case ISD::FrameIndex:
+ assert(0 && "ISD::FrameIndex Unimplemented");
abort();
case ISD::GlobalAddress: {
GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
- unsigned Tmp1 = MakeReg(MVT::i32);
+ Tmp1 = MakeReg(MVT::i32);
BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
.addGlobalAddress(GV);
if (GV->hasWeakLinkage() || GV->isExternal()) {
@@ -990,7 +1006,23 @@
return Result;
case ISD::ADD_PARTS:
- case ISD::SUB_PARTS:
+ case ISD::SUB_PARTS: {
+ assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
+ "Not an i64 add/sub!");
+ // Emit all of the operands.
+ std::vector<unsigned> InVals;
+ for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
+ InVals.push_back(SelectExpr(N.getOperand(i)));
+ if (N.getOpcode() == ISD::ADD_PARTS) {
+ BuildMI(BB, PPC::ADDC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
+ BuildMI(BB, PPC::ADDE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
+ } else {
+ BuildMI(BB, PPC::SUBFC, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
+ BuildMI(BB, PPC::SUBFE, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
+ }
+ return Result+N.ResNo;
+ }
+
case ISD::UREM:
case ISD::SREM:
case ISD::SDIV:
Index: llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp
diff -u llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.129 llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.130
--- llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp:1.129 Fri Mar 25 19:28:05 2005
+++ llvm/lib/Target/PowerPC/PPC32ISelSimple.cpp Mon Mar 28 16:28:37 2005
@@ -2392,7 +2392,7 @@
PPC::ADD, PPC::SUB, PPC::AND, PPC::OR, PPC::XOR
};
static const unsigned LongOpTab[2][5] = {
- { PPC::ADDC, PPC::SUBC, PPC::AND, PPC::OR, PPC::XOR },
+ { PPC::ADDC, PPC::SUBFC, PPC::AND, PPC::OR, PPC::XOR },
{ PPC::ADDE, PPC::SUBFE, PPC::AND, PPC::OR, PPC::XOR }
};
Index: llvm/lib/Target/PowerPC/PowerPCInstrInfo.td
diff -u llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.50 llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.51
--- llvm/lib/Target/PowerPC/PowerPCInstrInfo.td:1.50 Tue Feb 15 14:26:49 2005
+++ llvm/lib/Target/PowerPC/PowerPCInstrInfo.td Mon Mar 28 16:28:37 2005
@@ -376,8 +376,6 @@
"subfe $rT, $rA, $rB">;
def SUB : XOForm_1r<31, 40, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
"sub $rT, $rA, $rB">;
-def SUBC : XOForm_1r<31, 8, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA, GPRC:$rB),
- "subc $rT, $rA, $rB">;
def ADDME : XOForm_3<31, 234, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
"addme $rT, $rA">;
def ADDZE : XOForm_3<31, 202, 0, 0, 0, 0, (ops GPRC:$rT, GPRC:$rA),
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